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SafeSU: an extended statistics unit for multicore timing interference

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10.1109/ETS50041.2021.9465444
 
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hdl:2117/352123

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Cabo Pitarch, Guillem
Bas Jalón, Francisco
Lorenzo Ortega, Rubén
Trilla Rodríguez, David
Alcaide Portet, SergiMés informacióMés informació
Moreto Planas, MiquelMés informacióMés informacióMés informació
Hernández Luz, Carles
Abella Ferrer, JaumeMés informació
Document typeConference report
Defense date2021
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
ProjectDe-RISC - De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer (EC-H2020-869945)
Abstract
Statistics units (SUs) in MPSoCs are becoming increasingly used for the (1) verification and (2) validation of multicore timing interference, as well as for (3) deploying safety measures in safety-related real-time systems. However, existing SU extensions to manage multicore timing interference have neither been integrated together nor deployed in commercial MPSoCs.This paper presents the realization of the Safe Statistics Unit (SafeSU for short), which smartly integrates existing solutions for multicore timing interference verification, validation and monitoring, and is in turn integrated in commercial space-graded RISC-V and SparcV8 MPSoCs. Our evaluation illustrates the operation of the SafeSU, and paves the way for a thorough validation prior to reaching commercialization and being offered as open source IP.
CitationCabo, G. [et al.]. SafeSU: an extended statistics unit for multicore timing interference. A: IEEE European Test Symposium. "2021 IEEE European Test Symposium, ETS 2021: May 24-28, 2021, Belgium: Proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 1-4. ISBN 978-1-6654-1849-2. DOI 10.1109/ETS50041.2021.9465444. 
URIhttp://hdl.handle.net/2117/352123
DOI10.1109/ETS50041.2021.9465444
ISBN978-1-6654-1849-2
Publisher versionhttps://ieeexplore.ieee.org/document/9465444
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  • Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [251]
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  • Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.874]
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