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  • Enabling Python to execute efficiently in heterogeneous distributed infrastructures with PyCOMPSs 

    Amela, Ramon; Ramón-Cortes, Cristian; Ejarque, Jorge; Conejero, Javier; Badia, Rosa M. (Association for Computing Machinery (ACM), 2017-11)
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    Python has been adopted as programming language by a large number of scientific communities. Additionally to the easy programming interface, the large number of libraries and modules that have been made available by a large ...
  • Leveraging Cloud Heterogeneity for Cost-Efficient Execution of Parallel Applications 

    Roloff, Eduardo; Diener, Matthias; Diaz Carreño, Emmanuell; Gaspary, Luciano Paschoal; Navaux, Philippe O.A. (Springer, 2017-08-01)
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    Public cloud providers offer a wide range of instance types, with different processing and interconnection speeds, as well as varying prices. Furthermore, the tasks of many parallel applications show different computational ...
  • SEDEA: A sensible approach to account DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
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    As the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy ...
  • Improving the integration of task nesting and dependencies in OpenMP 

    Pérez, Josep M.; Beltran, Vicenç; Labarta, Jesús; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
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    The tasking model of OpenMP 4.0 supports both nesting and the definition of dependences between sibling tasks. A natural way to parallelize many codes with tasks is to first taskify the high-level functions and then to ...
  • Picos, a hardware task-dependence manager for task-based dataflow programming models 

    Tan, Xubin; Bosch, Jaume; Vidal, Miquel; Álvarez, Carlos; Jiménez-González, Daniel; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
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    Task-based programming Task-based programming models such as OpenMP, Intel TBB and OmpSs are widely used to extract high level of parallelism of applications executed on multi-core and manycore platforms. These programming ...
  • HetFS: A heterogeneous file system for everyone 

    Koloventzos, Georgios; Nou, Ramon; Miranda, Alberto; Cortés, Toni (Springer, 2017)
    Texto en actas de congreso
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    Storage devices have been getting more and more diverse during the last decade. The advent of SSDs made it painfully clear that rotating devices, such as HDDs or magnetic tapes, were lacking in regards to response time. ...
  • Integrating memory perspective into the BSC performance tools 

    Servat, Harald; Labarta Mancho, Jesús José; Hoppe, Hans-Christian; Gimenez, Judit; Peña, Antonio J. (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    The growing gap between processor and memory speeds results in complex memory hierarchies as processors evolve to mitigate such differences by taking advantage of locality of reference. In this direction, the BSC performance ...
  • Exploiting key-value data stores scalability for HPC 

    Cugnasco, Cesare; Becerra Fontal, Yolanda; Torres Viñals, Jordi; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
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    BigData revolutionised the IT industry. It first interested the OLTP systems. Distributed Hash Tables replaced Traditional SQL databases as they guaranteed low response time on simple read/write requests. The second wave ...
  • Beyond the socket: NUMA-aware GPUs 

    Ugljesa, Milic; Villa, Oreste; Bolotin, Evgeny; Arunkumar, Akhil; Ebrahimi, Eiman; Jaleel, Aamer; Ramirez, Alex; Nellans, David (Association for Computing Machinery, 2017-10)
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    GPUs achieve high throughput and power efficiency by employing many small single instruction multiple thread (SIMT) cores. To minimize scheduling logic and performance variance they utilize a uniform memory system and ...
  • Is Arm software ecosystem ready for HPC? 

    Banchelli Gracia, Fabio F.; Ruiz, Daniel; Hao Xu Lin, Ying; Mantovani, Filippo (2017-11-14)
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    In recent years, the HPC community has increasingly grown its interest towards the Arm architecture with research projects targeting primarily the installation of Arm-based clusters. State of the art research project ...
  • Enabling a reliable STT-MRAM main memory simulation 

    Asifuzzaman, Kazi; Sánchez-Verdejo, Rommel; Radojković, Petar (Association for Computing Machinery, 2017-10)
    Comunicación de congreso
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    STT-MRAM is a promising new memory technology with very desirable set of properties such as non-volatility, byte-addressability and high endurance. It has the potential to become the universal memory that could be incorporated ...
  • Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach 

    Rigo, Alvise; Pinto, Christian; Pouget, Kevin; Raho, Daniel; Dutoit, Denis; Martinez, Pierre-Yves; Doran, Chris; Benini, Luca; Mavroidis, Iakovos; Marazakis, Manolis; Bartsch, Valeria; Lonsdale, Guy; Pop, Antoniu; Goodacre, John; Colliot, Annaïk; Carpenter, Paul; Radojkovic, Petar; Pleiter, Dirk; Drouin, Dominique; Dupont de Dinechin, Benoît (IEEE, 2017-09-28)
    Comunicación de congreso
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    Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able ...

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