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Recent Submissions
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The case for data centre hyperloops
(Institute of Electrical and Electronics Engineers (IEEE), 2024)
Conference report
Open AccessData movement is a hot-button topic today, with workloads like machine learning (ML) training, graph processing, and data analytics consuming datasets as large as 30PB. Such a dataset would take almost a week to transfer ... -
Hypervisor extension for a RISC-V processor
(2023)
Conference lecture
Open AccessThis paper describes our experience implementing a Hypervisor extension for a 64-bit RISC-V processor. We describe the design process and the main required parts with a brief explanation of each one. -
Practically tackling memory bottlenecks of graph-processing workloads
(Institute of Electrical and Electronics Engineers (IEEE), 2024)
Conference report
Open AccessGraph-processing workloads have become widespread due to their relevance on a wide range of application domains such as network analysis, path- planning, bioinformatics, and machine learning. Graph-processing workloads ... -
Enabling high-level parallel programming on multi-FPGA clusters
(Association for Computing Machinery (ACM), 2024)
Conference report
Open AccessField Programmable Gate Arrays (FPGA) are still relatively new in the High Performance Computing (HPC) field. Hence, they still lack a mature ecosystem that allows non-FPGA experts to scale an application with many devices ... -
Extending the OCATA digital twin for optical connections based on digital subcarrier multiplexing
(Institute of Electrical and Electronics Engineers (IEEE), 2024)
Conference report
Open AccessTime-domain digital twin models for single carrier and DSCM signals are developed that propagate features to estimate the impact of filter penalties on the BER. Results show remarkable accuracy, which is used for lightpath ... -
NeRFLight: Fast and Light Neural Radiance Fields using a shared feature grid
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessWhile original Neural Radiance Fields (NeRF) have shown impressive results in modeling the appearance of a scene with compact MLP architectures, they are not able to achieve real-time rendering. This has been recently ... -
Harnessing the computing continuum across personalized healthcare, maintenance and inspection, and Farming 4.0
(SciTePress, 2024)
Conference report
Open AccessThe AI-SPRINT project, launched in 2021 and funded by the European Commission, focuses on the development and implementation of AI applications across the computing continuum. This continuum ensures the coherent integration ... -
ALPI: Enhancing portability and interoperability of task-aware libraries
(2024)
Conference report
Restricted access - publisher's policyTask-based programming models are a promising approach to exploiting complex distributed and heterogeneous systems. However, integrating different communication, offloading, and storage APIs within tasks poses performance ... -
Makinote: An FPGA-based HW/SW platform for pre-silicon emulation of RISC-V designs
(Association for Computing Machinery (ACM), 2024)
Conference report
Open AccessEmulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable ... -
eProcessor: European, extendable, energy-efficient, extreme-scale, extensible, processor ecosystem
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessThe eProcessor project aims at creating a RISC-V full stack ecosystem. The eProcessor architecture combines a high-performance out-of-order core with energy-efficient accelerators for vector processing and artificial ... -
Efficient diverse redundant DNNs for autonomous driving
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessAutomotive applications with safety requirements must adhere to specific regulations such as ISO 26262, which imposes the use of diverse redundancy for the highest integrity levels (i.e., ASIL D). While this has been often ... -
Software development vehicles to enable extended and early co-design: a RISC-V and HPC case of study
(Springer, 2023)
Conference report
Open AccessPrototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., compiler developers), and early adopters from the ...
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