Exploració per autor "Hernández Luz, Carles"
Ara es mostren els items 1-20 de 30
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A safety-critical, RISC-V SoC integrated and ASIC-ready classic McEliece accelerator
(Springer, 2024)
Text en actes de congrés
Accés restringit per política de l'editorialSecurity is an integral part of ensuring the integrity of safety-critical systems. Safety-critical systems with extremely long-lifespan, such as the ones employed in the space and automotive industry, need additional ... -
A security model for randomization-based protected caches
(2022)
Article
Accés obertCache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several ... -
Accurately measuring contention in Mesh NoCs in time-sensitive embedded systems
(Association for Computing Machinery (ACM), 2023-05)
Article
Accés obertThe computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous ... -
Achieving diverse redundancy for GPU Kernels
(Institute of Electrical and Electronics Engineers (IEEE), 2022-04)
Article
Accés obertAutonomous driving requires high-performance computing devices including general-purpose CPUs as well as specific accelerators, with GPUs having a key role due to their flexibility. Safety-critical microcontrollers have ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An approach for detecting power peaks during testing and breaking systematic pathological behavior
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThe verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ... -
Cache side-channel attacks and time-predictability in high-performance critical real-time systems
(Association for Computing Machinery (ACM), 2018-06-24)
Comunicació de congrés
Accés obertEmbedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ... -
Challenges in deeply heterogeneous high performance systems
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertRECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Comunicació de congrés
Accés obertThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
Enabling hardware randomization across the cache hierarchy in Linux-Class processors
(2020)
Text en actes de congrés
Accés obertThe most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied ... -
End-to-end QoS for the open source safety-relevant RISC-V SELENE platform
(arXiv, 2022)
Text en actes de congrés
Accés obertThis paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ... -
EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems
(2018-07-17)
Article
Accés obertThe increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ... -
High-integrity GPU designs for critical real-time automotive systems
(Barcelona Supercomputing Center, 2019-05-07)
Text en actes de congrés
Accés obert -
HLS-based HW/SW co-design of the post-quantum classic McEliece cryptosystem
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertWhile quantum computers are rapidly becoming more powerful, the current cryptographic infrastructure is imminently threatened. In a preventive manner, the U.S. National Institute of Standards and Technology (NIST) has ... -
Locality-aware cache random replacement policies
(2019-02-01)
Article
Accés obertMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Modeling the impact of process variations in worst-case energy consumption estimation
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThe advent of autonomous power-limited systems poses a new challenge for system verification. Powerful processors needed to enable autonomous operation, are typically power-hungry, jeopardizing battery duration. Therefore, ... -
NoCo: ILP-based worst-case contention estimation for mesh real-time manycores
(IEEE, 2019-01-07)
Comunicació de congrés
Accés obertManycores are capable of providing the computational demands required by functionally-advanced critical applications in domains such as automotive and avionics. In manycores a network-on-chip (NoC) provides access to shared ... -
Predictive reliability and fault management in exascale systems: State of the art and perspectives
(2020-09)
Article
Accés obertPerformance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due ... -
Randomization for safer, more reliable and secure, high-performance automotive processors
(Institute of Electrical and Electronics Engineers (IEEE), 2019-12)
Article
Accés obertThe automotive domain is witnessing a relentless transition to autonomous cars demanding high-performance processors to timely execute complex, critical, decision-making software. The other side of the coin is that ... -
RPR: a random replacement policy with limited pathological replacements
(Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialMeasurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...
