Now showing items 1-20 of 30

    • A safety-critical, RISC-V SoC integrated and ASIC-ready classic McEliece accelerator 

      Kostalabros, Vatistas; Ribes González, Jordi; Farràs Ventura, Oriol; Moretó Planas, Miquel; Hernández Luz, Carles (Springer, 2024)
      Conference report
      Restricted access - publisher's policy
      Security is an integral part of ensuring the integrity of safety-critical systems. Safety-critical systems with extremely long-lifespan, such as the ones employed in the space and automotive industry, need additional ...
    • A security model for randomization-based protected caches 

      Ribes González, Jordi; Farràs Ventura, Oriol; Hernández Luz, Carles; Kostalabros, Vatistas; Moretó Planas, Miquel (2022)
      Article
      Open Access
      Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention. This vulnerability has been shown to lead to several ...
    • Accurately measuring contention in Mesh NoCs in time-sensitive embedded systems 

      Cardona Nadal, Jordi; Hernández Luz, Carles; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023-05)
      Article
      Open Access
      The computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous ...
    • Achieving diverse redundancy for GPU Kernels 

      Alcaide Portet, Sergi; Kosmidis, Leonidas; Hernández Luz, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2022-04)
      Article
      Open Access
      Autonomous driving requires high-performance computing devices including general-purpose CPUs as well as specific accelerators, with GPUs having a key role due to their flexibility. Safety-critical microcontrollers have ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
    • An approach for detecting power peaks during testing and breaking systematic pathological behavior 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ...
    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
      Conference lecture
      Open Access
      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
    • Challenges in deeply heterogeneous high performance systems 

      Agosta, Giovanni; Fornaciari, William; Atienza, David; Canal Corretger, Ramon; Cilardo, Alessandro; Flich Cardo, José; Hernández Luz, Carles; Kulczewski, Michal; Massari, Giuseppe; Tornero Gavilá, Rafael; Zapater Sancho, Marina (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      RECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a recently started project funded within the H2020 FETHPC programme, which is expressly targeted at exploring ...
    • DVINO: A RISC-V vector processor implemented in 65nm technology 

      Cabo Pitarch, Guillem; Candon, Gerard; Carril, Xavier; Doblas Font, Max; Dominguez de la Rocha, Marc; González Trejo, Alberto; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel Israel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Minervini Minervini, Francesco; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas, Narcis; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruíz Ramírez, Abraham Josafat; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Figueras Bagué, Roger; Fontova, Pau; Marimon Illana, Joan; Montabes, Víctor; Cristal Kestelman, Adrián; Hernández Luz, Carles; Moretó Planas, Miquel; Moll Echeto, Francisco de Borja; Palomar Pérez, Óscar; Rubio Sola, Jose Antonio; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference lecture
      Open Access
      This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ...
    • Enabling hardware randomization across the cache hierarchy in Linux-Class processors 

      Doblas, Max; Kostalampros, Ioannis-Vatistas; Moretó Planas, Miquel; Hernández Luz, Carles (2020)
      Conference report
      Open Access
      The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied ...
    • End-to-end QoS for the open source safety-relevant RISC-V SELENE platform 

      Andreu Cerezo, Pablo; Hernández Luz, Carles; Picornell Sanjuan, Tomás; López Rodríguez, Pedro; Alcaide Portet, Sergi; Bas Jalón, Francisco; Benedicte Illescas, Pedro; Chang, Feng; Cabo Pitarch, Guillem; Fuentes Díaz, Francisco Javier; Abella Ferrer, Jaume (arXiv, 2022)
      Conference report
      Open Access
      This paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ...
    • EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems 

      Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
      Article
      Open Access
      The increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ...
    • High-integrity GPU designs for critical real-time automotive systems 

      Alcaide, Sergi; Kosmidis, Leonidas; Hernández Luz, Carles; Abella Ferrer, Jaume (Barcelona Supercomputing Center, 2019-05-07)
      Conference report
      Open Access
    • HLS-based HW/SW co-design of the post-quantum classic McEliece cryptosystem 

      Kostalabros, Vatistas; Ribes González, Jordi; Farràs Ventura, Oriol; Moretó Planas, Miquel; Hernández Luz, Carles (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      While quantum computers are rapidly becoming more powerful, the current cryptographic infrastructure is imminently threatened. In a preventive manner, the U.S. National Institute of Standards and Technology (NIST) has ...
    • Locality-aware cache random replacement policies 

      Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2019-02-01)
      Article
      Open Access
      Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ...
    • Modeling the impact of process variations in worst-case energy consumption estimation 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      The advent of autonomous power-limited systems poses a new challenge for system verification. Powerful processors needed to enable autonomous operation, are typically power-hungry, jeopardizing battery duration. Therefore, ...
    • NoCo: ILP-based worst-case contention estimation for mesh real-time manycores 

      Cardona Nadal, Jordi; Hernández Luz, Carles; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (IEEE, 2019-01-07)
      Conference lecture
      Open Access
      Manycores are capable of providing the computational demands required by functionally-advanced critical applications in domains such as automotive and avionics. In manycores a network-on-chip (NoC) provides access to shared ...
    • Predictive reliability and fault management in exascale systems: State of the art and perspectives 

      Canal Corretger, Ramon; Hernández Luz, Carles; Tornero Gavilá, Rafael; Cilardo, Alessandro; Massari, Giuseppe; Reghenzani, Federico; Fornaciari, William; Zapater Sancho, Marina; Atienza, David; Oleksiak, Ariel; Wojciech Piatek, Poznan; Abella Ferrer, Jaume (2020-09)
      Article
      Open Access
      Performance and power constraints come together with Complementary Metal Oxide Semiconductor technology scaling in future Exascale systems. Technology scaling makes each individual transistor more prone to faults and, due ...
    • Randomization for safer, more reliable and secure, high-performance automotive processors 

      Trilla Rodríguez, David; Cazorla Almeida, Francisco Javier; Hernández Luz, Carles; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2019-12)
      Article
      Open Access
      The automotive domain is witnessing a relentless transition to autonomous cars demanding high-performance processors to timely execute complex, critical, decision-making software. The other side of the coin is that ...
    • RPR: a random replacement policy with limited pathological replacements 

      Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018)
      Conference report
      Restricted access - publisher's policy
      Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...