Recent Submissions

  • Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel 

    Escuín Blasco, Carlos; Monreal Arnal, Teresa; Llaberia Griñó, José M.; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Victor (Sociedad de Arquitectura y Tecnología de Computadores (SARTECO), 2021)
    Conference report
    Open Access
    La degradación debida a las escrituras que sufren las bitcells implementadas con tecnologi´as de memoria no volátil (NVM) es uno de los principales escollos que se presentan a la hora de construir la cache de último nivel ...
  • Microarchitectural design-space exploration of an in-order RISC-V processor in a 22nm CMOS technology 

    Doblas Font, Max; Wright, Andrew; Sonmez, Nehir; Moreto Planas, Miquel; Arvind (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2021)
    Conference lecture
    Open Access
    The purpose of this paper is to explore the trade-offs between IPC and maximum clock frequency in an in-order processor design. This work evaluates the impact on the performance and frequency of different pipeline ...
  • An oracle for guiding large-scale model/hybrid parallel training of convolutional neural networks 

    Njoroge Kahira, Albert; Nguyen, Truong Thao; Bautista Gomez, Leonardo Arturo; Takano, Ryousei; Badia Sala, Rosa Maria; Wahib, Mohamed (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2021)
    Conference lecture
    Open Access
    Deep Neural Network (DNN) frameworks use distributed training to enable faster time to convergence and alleviate memory capacity limitations when training large models and/or using high dimension inputs. With the steady ...
  • PrioRAT: criticality-driven prioritization inside the on-chip memory hierarchy 

    Dimic, Vladimir; Moreto Planas, Miquel; Casas Guix, Marc; Valero Cortés, Mateo (Springer Nature, 2021)
    Conference report
    Open Access
    The ever-increasing gap between the processor and main memory speeds requires careful utilization of the limited memory link. This is additionally emphasized for the case of memory-bound applications. Prioritization of ...
  • How2Sign: A large-scale multimodal dataset for continuous American sign language 

    Cardoso Duarte, Amanda; Palaskar, Shruti; Ventura Ripol, Lucas; Ghadiyaram, Deepti; DeHaan, Kenneth; Metze, Florian; Torres Viñals, Jordi; Giró Nieto, Xavier (Institute of Electrical and Electronics Engineers (IEEE), 2021)
    Conference lecture
    Open Access
    One of the factors that have hindered progress in the areas of sign language recognition, translation, and production is the absence of large annotated datasets. Towards this end, we introduce How2Sign, a multimodal and ...
  • gem5 + rtl: A framework to enable RTL models inside a full-system simulator 

    López Paradís, Guillem; Armejach Sanosa, Adrià; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2021)
    Conference report
    Open Access
    In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system ...
  • Combining dynamic concurrency throttling with voltage and frequency scaling on task-based programming models 

    Navarro Muñoz, Antoni; Lorenzon, Arthur F.; Ayguadé Parra, Eduard; Beltran Querol, Vicenç (Association for Computing Machinery (ACM), 2021)
    Conference report
    Open Access
    Being on the verge of exascale performance has shifted the prioritization of performance in applications to the inclusion of power-performance efficiency as a primary objective in the High Performance Computing (HPC) ...
  • PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip 

    Monemi, Alireza; Pérez Gallardo, Iván; Leyva Santes, Neiel; Vallejo Gutiérrez, Enrique; Beivide Palacio, Julio Ramon; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2021)
    Conference report
    Open Access
    The integration of many processing elements per die makes it more difficult to provide low latency in the Network-on-Chip (NoC). Multihop bypass proposals, such as SMART, attack this problem by allowing flits to skip ...
  • Organization component analysis: The method for extracting insights from the shape of cluster 

    Mahdavi, Kaveh; Labarta Mancho, Jesús José; Giménez Lucas, Judit (Institute of Electrical and Electronics Engineers (IEEE), 2021)
    Conference report
    Open Access
    Clustering analysis is widely used to stratify data in the same cluster when they are similar according to specific metrics. The process of understanding and interpreting clusters is mostly intuitive. However, we observe ...
  • Assessing and improving the suitability of model-based design for GPU-accelerated railway control systems 

    Calderón Torres, Alejandro Josué; Kosmidis, Leonidas; Nicolás Ramírez, Carlos Fernando; Lasala, Javier de; Larrañaga, Ion (Springer Nature, 2021)
    Conference report
    Open Access
    Model-Based Design (MBD) is widely used for the design and simulation of electric traction control systems in the railway industry. Moreover, similar to other transportation industries, railway is moving towards the ...
  • The DeepHealth Toolkit: A unified framework to boost biomedical applications 

    Cancilla, Michele; Canalini, Laura; Bolelli, Federico; Allegretti, Stefano; Carrión Ponz, Salvador; Paredes Palacios, Roberto; Gómez Adrián, Jon A.; Leo, Simone; Piras, Marco Enrico; Pireddu, Luca; Badouh, Asaf; Marco-Sola, Santiago; Álvarez Martí, Lluc; Moreto Planas, Miquel; Grana, Costantino (Institute of Electrical and Electronics Engineers (IEEE), 2021)
    Conference report
    Open Access
    Given the overwhelming impact of machine learning on the last decade, several libraries and frameworks have been developed in recent years to simplify the design and training of neural networks, providing array-based ...
  • Mont-Blanc 2020: Towards scalable and power efficient European HPC processors 

    Armejach Sanosa, Adrià; Brank, Bine; Cortina Guardia, Jordi; Dolique, François; Hayes, Timothy; Ho, Nam; Lagadec, Pierre-Axel; Lemaire, Romain; López Paradís, Guillem; Marliac, Laurent; Moreto Planas, Miquel; Marcuello Pascual, Pedro; Pleiter, Dirk; Tan, Xubin; Derradji, Said (Institute of Electrical and Electronics Engineers (IEEE), 2021)
    Conference report
    Open Access
    The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European ...

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