Enviaments recents

  • GekkoFS: A temporary distributed file system for HPC applications 

    Vef, Marc-André; Moti, Nafiseh; Süb, Tim; Tocci, Tommaso; Nou, Ramon; Miranda, Alberto; Cortés, Toni; Brinkmann, Andre (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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    We present GekkoFS, a temporary, highly-scalable burst buffer file system which has been specifically optimized for new access patterns of data-intensive High-Performance Computing (HPC) applications. The file system ...
  • Runtime-assisted cache coherence deactivation in task parallel programs 

    Caheny, Paul; Álvarez, Lluc; Valero Cortés, Mateo; Moreto Planas, Miquel; Casas, Marc (Association for Computing Machinery (ACM), 2018)
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    With increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data ...
  • Stencil codes on a vector length agnostic architecture 

    Armejach Sanosa, Adrià; Caminal Pallarés, Helena; Cebrián González, Juan Manuel; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero Cortés, Mateo; Casas, Marc; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2018)
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    Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...
  • Improving the interoperability between MPI and task-based programming models 

    Sala, Kevin; Bellón, Jorge; Farré, Pau; Teruel, Xavier; Pérez, Josep M.; Peña, Antonio J.; Holmes, Daniel; Beltran, Vicenç; Labarta Mancho, Jesús José (Association for Computing Machinery (ACM), 2018)
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    In this paper we propose an API to pause and resume task execution depending on external events. We leverage this generic API to improve the interoperability between MPI synchronous communication primitives and tasks. When ...
  • Runtime-guided management of stacked DRAM memories in task parallel programs 

    Álvarez, Lluc; Casas, Marc; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2018)
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    Stacked DRAM memories have become a reality in High-Performance Computing (HPC) architectures. These memories provide much higher bandwidth while consuming less power than traditional off-chip memories, but their limited ...
  • Reducing data movement on large shared memory systems by exploiting computation dependencies 

    Barrera, I.S.; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moreto Planas, Miquel; Labarta Mancho, Jesús José; Casas Guix, Marc (Association for Computing Machinery (ACM), 2018)
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    Shared memory systems are becoming increasingly complex as they typically integrate several storage devices. That brings different access latencies or bandwidth rates depending on the proximity between the cores where ...
  • Variable batched DGEMM 

    Valero-Lara, Pedro; Martinez-Perez, Ivan; Mateo, Sergio; Sirvent Pardell, Raül; Beltran Querol, Vicenç; Martorell Bofill, Xavier; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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    Many scientific applications are in need to solve a high number of small-size independent problems. These individual problems do not provide enough parallelism and then, these must be computed as a batch. Today, vendors ...
  • Performance characterization of spark workloads on shared NUMA Systems 

    Baig, Shuja Ur Rehman; Amaral, Marcelo; Polo Cantero, José; Carrera Pérez, David (Institute of Electrical and Electronics Engineers (IEEE), 2018)
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    As the adoption of Big Data technologies becomes the norm in an increasing number of scenarios, there is also a growing need to optimize them for modern processors. Spark has gained momentum over the last few years among ...
  • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

    Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
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    High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...
  • RPR: a random replacement policy with limited pathological replacements 

    Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018)
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    Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...
  • HPC benchmarking: scaling right and looking beyond the average 

    Radulovic, Milan; Asifuzzaman, Kazi; Carpenter, Paul Matthew; Radojkovic, Petar; Ayguadé Parra, Eduard (Springer, 2018)
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    Designing a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the ...
  • Detection-aided liver lesion segmentation using deep learning 

    Bellver, Míriam; Maninis, Kevis-Kokitsi; Pont Tuset, Jordi; Giró Nieto, Xavier; Torres Viñals, Jordi; Van Gool, Luc (2017)
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    A fully automatic technique for segmenting the liver and localizing its unhealthy tissues is a convenient tool in order to diagnose hepatic diseases and assess the response to the according treatments. In this work we ...

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