Browsing by Author "Moreto Planas, Miquel"
Now showing items 1-20 of 91
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A case for code-representative microbenchmarks
(Barcelona Supercomputing Center, 2017-05-04)
Conference report
Open AccessMicrobenchmarks are fundamental in the design of a microarchitecture. They allow rapid evaluation of the system, while incurring little exploration overhead. One key design aspect is the thermal design point (TDP), the ... -
A FM-index transformation to enable large k-steps
(Barcelona Supercomputing Center, 2019-05-07)
Conference report
Open Access -
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
(ACM, 2013)
Conference report
Open AccessComputing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ... -
A hardware/software co-design of K-mer counting using a CAPI-enabled FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessAdvances in Next Generation Sequencing (NGS) technologies have caused the proliferation of genomic applications to detect DNA mutations and guide personalized medicine. These applications have an enormous computational ... -
A vulnerability factor for ECC-protected memory
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessFault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected ... -
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessRecent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ... -
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7
(2015)
Conference report
Open Access -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An optimized predication execution for SIMD extensions
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference lecture
Open AccessVector processing is a widely used technique to improve performance and energy efficiency in modern processors. Most of them rely on predication to support divergence control. However, performance and energy consumption ... -
Architectural support for task dependence management with flexible software scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessThe growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ... -
Asynchronous and exact forward recovery for detected errors in iterative solvers
(2018-03-19)
Article
Open AccessCurrent trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ... -
ATM: approximate task memoization in the runtime system
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessRedundant computations appear during the execution of real programs. Multiple factors contribute to these unnecessary computations, such as repetitive inputs and patterns, calling functions with the same parameters or bad ... -
BST: A BookSim-based toolset to simulate NoCs with single- and multi-hop bypass
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessNetwork-on-Chips are a critical part of modern multiprocessors and their relevance will grow with the number of cores. The development of future NoC designs relies on detailed simulation models that accurately estimate ... -
CATA: Criticality aware task acceleration for multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessManaging criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
(Association for Computing Machinery (ACM), 2015)
Conference report
Open AccessThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
Compressed sparse FM-index: Fast sequence alignment using large K-steps
(2020-06-05)
Article
Open AccessThe FM-index is a data structure used in genomics for exact search of input sequences over large reference genomes. Algorithms based on the FM-index show an irregular memory access pattern, resulting in a memory bound ... -
CPU accounting in CMP processors
(2009-01)
Article
Open AccessChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
Design space exploration of next-generation HPC machines
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Restricted access - confidentiality agreementThe landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers ... -
Design trade-offs for emerging HPC processors based on mobile market technology
(2019-09-01)
Article
Open AccessHigh-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
(2016-12)
Article
Open AccessAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ...
