Now showing items 1-20 of 85

    • A case for code-representative microbenchmarks 

      Bulla, Calvin; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2017-05-04)
      Conference report
      Open Access
      Microbenchmarks are fundamental in the design of a microarchitecture. They allow rapid evaluation of the system, while incurring little exploration overhead. One key design aspect is the thermal design point (TDP), the ...
    • A FM-index transformation to enable large k-steps 

      Langarita, Rubén; Armejach Sanosa, Adrià; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
      Conference report
      Open Access
    • A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness 

      Cook, Henry; Moreto Planas, Miquel; Bird, Sarah L.; Dao, Khanh; Patterson, David; Asanovic, Krste (ACM, 2013)
      Conference report
      Open Access
      Computing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ...
    • A vulnerability factor for ECC-protected memory 

      Jaulmes, Luc Etienne; Moreto Planas, Miquel; Valero Cortés, Mateo; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      Fault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected ...
    • Adapting cache partitioning algorithms to pseudo-LRU replacement policies 

      Kedzierski, Kamil; Moreto Planas, Miquel; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2010)
      Conference report
      Open Access
      Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ...
    • Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7 

      Prat Robles, David; Ortega Carrasco, Cristobal; Casas Guix, Marc; Moreto Planas, Miquel; Valero Cortés, Mateo (2015)
      Conference report
      Open Access
    • An optimized predication execution for SIMD extensions 

      Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Moreto Planas, Miquel; Casas Guix, Marc; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference lecture
      Open Access
      Vector processing is a widely used technique to improve performance and energy efficiency in modern processors. Most of them rely on predication to support divergence control. However, performance and energy consumption ...
    • Architectural support for task dependence management with flexible software scheduling 

      Castillo, Emilio; Álvarez Martí, Lluc; Moreto Planas, Miquel; Casas, Marc; Vallejo, Enrique; Bosque, Jose L.; Beivide Palacio, Ramon; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      The growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ...
    • Asynchronous and exact forward recovery for detected errors in iterative solvers 

      Jaulmes, Luc Etienne; Casas, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2018-03-19)
      Article
      Open Access
      Current trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ...
    • ATM: approximate task memoization in the runtime system 

      Brumar, Iulian; Casas, Marc; Moreto Planas, Miquel; Valero Cortés, Mateo; Sohi, Gurindar S. (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Redundant computations appear during the execution of real programs. Multiple factors contribute to these unnecessary computations, such as repetitive inputs and patterns, calling functions with the same parameters or bad ...
    • CATA: Criticality aware task acceleration for multicore processors 

      Castillo, Emilio; Moreto Planas, Miquel; Casas, Marc; Álvarez Martí, Lluc; Vallejo, Enrique; Chronaki, Kallia; Badia Sala, Rosa Maria; Bosque Orero, José Luis; Beivide Palacio, Julio Ramón; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ...
    • Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures 

      Álvarez Martí, Lluc; Vilanova, Lluís; Moreto Planas, Miquel; Casas, Marc; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
      Conference report
      Open Access
      The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ...
    • CPU accounting in CMP processors 

      Luque, Carlos; Moreto Planas, Miquel; Cazorla, Francisco; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (2009-01)
      Article
      Open Access
      Chip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ...
    • Design space exploration of next-generation HPC machines 

      Gómez Crespo, Constantino; Martínez Palau, Francesc; Armejach Sanosa, Adrià; Moreto Planas, Miquel; Mantovani, Filippo; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Restricted access - confidentiality agreement
      The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers ...
    • Design trade-offs for emerging HPC processors based on mobile market technology 

      Armejach Sanosa, Adrià; Casas, Marc; Moreto Planas, Miquel (2019-09-01)
      Article
      Open Access
      High-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ...
    • DReAM: An approach to estimate per-Task DRAM energy in multicore systems 

      Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2016-12)
      Article
      Open Access
      Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ...
    • DReAM: Per-task DRAM energy metering in multicore systems 

      Liu, Qixiao; Moreto Planas, Miquel; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (Springer, 2014)
      Conference report
      Open Access
      Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ...
    • Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies 

      Barredo Ferreira, Adrián; Cebrián González, Juan Manuel; Valero Cortés, Mateo; Casas Guix, Marc; Moreto Planas, Miquel (2020-03)
      Article
      Open Access
      Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal ...
    • Enabling hardware randomization across the cache hierarchy in Linux-Class processors 

      Doblas, Max; Kostalabros, Ioannis-Vatistas; Moreto Planas, Miquel; Hernández Luz, Carles (2020)
      Conference report
      Open Access
      The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied ...
    • Evaluating execution time predictability of task-based programs on multi-core processors 

      Grass, Thomas Dieter; Rico Carro, Alejandro; Casas Guix, Marc; Moreto Planas, Miquel; Ramírez Bellido, Alejandro (Springer, 2015)
      Conference report
      Restricted access - publisher's policy
      Task-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ...