Browsing by Author "Moreto Planas, Miquel"
Now showing items 1-20 of 62
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A case for code-representative microbenchmarks
(Barcelona Supercomputing Center, 2017-05-04)
Conference report
Open AccessMicrobenchmarks are fundamental in the design of a microarchitecture. They allow rapid evaluation of the system, while incurring little exploration overhead. One key design aspect is the thermal design point (TDP), the ... -
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Conference report
Open AccessRecent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache partitioning algorithms proposed so far assume Least ... -
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM Power7
(2015)
Conference report
Open Access -
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
(ACM, 2013)
Conference report
Open AccessComputing workloads often contain a mix of interactive, latency-sensitive foreground applications and recurring background computations. To guarantee responsiveness, interactive and batch applications are often run on ... -
Architectural support for task dependence management with flexible software scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessThe growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ... -
Asynchronous and exact forward recovery for detected errors in iterative solvers
(2018-03-19)
Article
Open AccessCurrent trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ... -
ATM: approximate task memoization in the runtime system
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessRedundant computations appear during the execution of real programs. Multiple factors contribute to these unnecessary computations, such as repetitive inputs and patterns, calling functions with the same parameters or bad ... -
CATA: Criticality aware task acceleration for multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessManaging criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ... -
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
(Association for Computing Machinery (ACM), 2015)
Conference report
Open AccessThe increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ... -
CPU accounting in CMP processors
(2009-01)
Article
Open AccessChip-MultiProcessors (CMP) introduce complexities when accounting CPU utilization to processes because the progress done by a process during an interval of time highly depends on the activity of the other processes it is ... -
DReAM: An approach to estimate per-Task DRAM energy in multicore systems
(2016-12)
Article
Open AccessAccurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is ... -
DReAM: Per-task DRAM energy metering in multicore systems
(Springer, 2014)
Conference report
Open AccessInteraction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, ... -
Evaluating execution time predictability of task-based programs on multi-core processors
(Springer, 2015)
Conference report
Restricted access - publisher's policyTask-based programming models are becoming increasingly important, as they can reduce the synchronization costs of parallel programs on multi-cores. Instances of the same task type in task-based programs consist of the ... -
Evaluating the impact of OpenMP 4.0 extensions on relevant parallel workloads
(Springer, 2015)
Conference report
Open AccessOpenMP has been for many years the most widely used programming model for shared memory architectures. Periodically, new features are proposed and some of them are finally selected for inclusion in the OpenMP standard. The ... -
Evolutionary system for prediction and optimization of hardware architecture performance
(2008-06)
Conference report
Open AccessThe design of computer architectures is a very complex problem. The multiple parameters make the number of possible combinations extremely high. Many researchers have used simulation, although it is a slow solution since ... -
Explaining dynamic cache partitioning speed ups
(2007-01)
Article
Open AccessCache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ... -
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers
(2015)
External research report
Open AccessThis paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ... -
Exploiting asynchrony from exact forward recovery for DUE in iterative solvers
(Association for Computing Machinery (ACM), 2015)
Conference report
Open AccessThis paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page ... -
Graph partitioning applied to DAG scheduling to reduce NUMA effects
(Association for Computing Machinery (ACM), 2018)
Conference lecture
Open AccessThe complexity of shared memory systems is becoming more relevant as the number of memory domains increases, with different access latencies and bandwidth rates depending on the proximity between the cores and the devices ... -
How can we improve energy efficiency through user-directed vectorization and task-based parallelization?
(Barcelona Supercomputing Center, 2015-05-05)
Open AccessHeterogeneity, parallelization and vectorization are key techniques to improve the performance and energy efficiency of modern computing systems. However, programming and maintaining code for these architectures poses a ...
