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dc.contributor.authorRatkovic, Ivan
dc.contributor.authorPalomar, Oscar
dc.contributor.authorStanic, Milan
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationRatkovic, I., Palomar, O., Stanic, M., Unsal, O., Cristal, A., Valero, M. A fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques. A: International Symposium on Low Power Electronics and Design. "ISLPED'16: proceedings of the 2016 International Symposium on Low Power Electronics and Design: San Francisco, USA: August 8-10, 2016". San Francisco, CA: Association for Computing Machinery (ACM), 2016, p. 362-367.
dc.description.abstractThe need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a power consuming functional unit, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. We perform this research in a fully parameterizable and automated fashion using various tools at both architectural and circuit levels.
dc.description.sponsorshipThe authors would like to thank to Borivoje Nikolic, Brian Richards, and Yunsup Lee for their useful advises and fruitful discussions. The research leading to these results has received funding from the RoMoL ERC Advanced Grant GA no 321253 and is supported in part by the European Union (FEDER funds) under contract TIN2015-65316-P. Ivan Ratkovic is supported by a FPU research grant from the Spanish MECD.
dc.format.extent6 p.
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Electrònica de potència
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshPower electronics
dc.subject.otherArithmetic and datapath circuits
dc.subject.otherPower and energy
dc.subject.otherMethodologies for EDA
dc.subject.otherSingle instruction
dc.subject.otherMultiple data
dc.titleA fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques
dc.typeConference report
dc.subject.lemacElectrònica de potència
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorRatkovic, I.; Palomar, O.; Stanic, M.; Unsal, O.; Cristal, A.; Valero, M.
local.citation.contributorInternational Symposium on Low Power Electronics and Design
local.citation.pubplaceSan Francisco, CA
local.citation.publicationNameISLPED'16: proceedings of the 2016 International Symposium on Low Power Electronics and Design: San Francisco, USA: August 8-10, 2016

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