Enviaments recents

  • Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems 

    Fernández de Lecea, Asier; Hassan, Mohamed; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Comunicació de congrés
    Accés obert
    Main memory is one of the most complex resources to analyze in multicore-based embedded real-time systems, with contention in the memory controller and the timing constraints of the main memory device as the main contributors ...
  • Time-predictable task-to-thread mapping in multi-core processors 

    Samadi, Mohammad; Royuela Alcázar, Sara; Pinho, Luis Miguel; Carvalho, Tiago; Quiñones, Eduardo (Elsevier, 2024)
    Article
    Accés obert
    The performance of time-predictable systems can be improved in multi-core processors using parallel programming models (e.g., OpenMP). However, schedulability analysis of parallel applications is a big challenge due to ...
  • Boosting HPC data analysis performance with the ParSoDA-Py library 

    Belcastro, Loris; Giampà, Salvatore; Marozzo, Fabrizio; Talia, Domenico; Trunfio, Paolo; Badia Sala, Rosa Maria; Ejarque, Jorge; Mammadli, Nihad (Springer, 2024-02)
    Article
    Accés obert
    Developing and executing large-scale data analysis applications in parallel and distributed environments can be a complex and time-consuming task. Developers often find themselves diverted from their application logic to ...
  • Assessing Saiph, a task-based DSL for high-performance computational fluid dynamics 

    Macià Sorrosal, Sandra; Martínez Ferrer, Pedro José; Ayguadé Parra, Eduard; Beltran Querol, Vicenç (Elsevier, 2023-10)
    Article
    Accés restringit per política de l'editorial
    Scientific applications face the challenge of efficiently exploiting increasingly complex parallel and distributed systems. Developing hand-tuned codes is a time-consuming, tedious and hardly reusable task. Reaching high ...
  • RISC-V for genome data analysis: opportunities and challenges 

    López Villellas, Lorien; Pineda Sánchez, Esteve; Badouh, Asaf; Marco-Sola, Santiago; Ibáñez Marín, Pablo; Alastruey Benedé, Jesús; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based ...
  • Explaining the behaviour of reinforcement learning agents in a multi-agent cooperative environment using policy graphs 

    Domènech Vila, Marc; Gnatyshak, Dmitry; Tormos Llorente, Adrián; Giménez Ábalos, Víctor; Álvarez Napagao, Sergio (2024-01-31)
    Article
    Accés obert
    The adoption of algorithms based on Artificial Intelligence (AI) has been rapidly increasing during the last few years. However, some aspects of AI techniques are under heavy scrutiny. For instance, in many use cases, it ...
  • NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS 

    Pavanello, Fabio; Marchand, Cedric; O’Connor, Ian; Orobtchouk, Regis; Mandorlo, Fabien; Letartre, Xavier; Cueff, Sebastien; Brando Guillaumes, Axel; Cazorla Almeida, Francisco Javier; Canal Corretger, Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. ...
  • O(n) key–value sort with active compute memory 

    Esmaili Dokht, Pouya; Guiot Cusido, Miquel; Radojkovic, Petar; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Adlard, Jason; Amato, Paolo; Sforzin, Marco (Institute of Electrical and Electronics Engineers (IEEE), 2024-02-29)
    Article
    Accés obert
    We propose the Active Compute Memory (ACM), a near-memory-processing architecture capable of performing key–value sort directly in the DRAM. In the ACM architecture, sort is merely the writing of data into memory with one ...
  • Lessons Learned from a Performance Analysis and Optimization of a Multiscale Cellular Simulation 

    Clasca, Marc; Garcia Gasulla, Marta; Montagud, Arnau; Carbonell Caballero, José; Valencia, Alfonso (Association for Computing Machinery (ACM), 2023)
    Comunicació de congrés
    Accés obert
    This work presents a comprehensive performance analysis and optimization of a multiscale agent-based cellular simulation. The optimizations applied are guided by detailed performance analysis and include memory management, ...
  • Uncertainty Management in Dependable and Intelligent Embedded Software 

    Perez Cerrolaza, Jon; Cazorla Almeida, Francisco Javier; Abella Ferrer, Jaume (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Article
    Accés obert
    The development of dependable and intelligent embedded systems progresses. However, integrating complex software stacks, machine learning solutions, and high-performance computing devices amplifies the functional and ...
  • End-to-End Workflows for Climate Science: Integrating HPC Simulations, Big Data Processing, and Machine Learning 

    Elia, Donatello; Scardigno, Sonia; Ejarque, Jorge; D'anca, Alessandro; Accarino, Gabriele; Scoccimarro, Enrico; Donno, Davide; Peano, Daniele; Immorlano, Francesco; Aloisio, Giovanni (Association for Computing Machinery (ACM), 2023)
    Comunicació de congrés
    Accés obert
    Current scientific workflow systems do not typically integrate simulation-centric and data-centric aspects due to their very different software/infrastructure requirements. A transparent integration of such components into ...
  • Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology 

    Doblas Font, Max; Candón Arenas, Gerard; Carril Gil, Xavier; Dominguez de la Rocha, Marc; Erra, Enric; González Trejo, Alberto; Jiménez, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Oltra Oltra, Josep Angel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas Quiroga, Narcís; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruiz Ramirez, Abraham Josafat; Safadi Figueroa, Hugo Ernesto; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Arreza, Fernando; Figueras Bagué, Roger; Fontova Muste, Pau; Marimon Illana, Joan; Aragonès Cervera, Xavier; Cristal Kestelman, Adrián; Mateo Peña, Diego; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Palomar Pérez, Óscar; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Comunicació de congrés
    Accés obert
    This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ...

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