A fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques
Document typeConference report
PublisherAssociation for Computing Machinery (ACM)
Rights accessRestricted access - publisher's policy
European Commisision's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a power consuming functional unit, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. We perform this research in a fully parameterizable and automated fashion using various tools at both architectural and circuit levels.
CitationRatkovic, I., Palomar, O., Stanic, M., Unsal, O., Cristal, A., Valero, M. A fully parameterizable low power design of vector fused multiply-add using active clock-gating techniques. A: International Symposium on Low Power Electronics and Design. "ISLPED'16: proceedings of the 2016 International Symposium on Low Power Electronics and Design: San Francisco, USA: August 8-10, 2016". San Francisco, CA: Association for Computing Machinery (ACM), 2016, p. 362-367.
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