Design and integration of hierarchical-placement multi-level caches for real-Time systems
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Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
Enabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, caches heavily complicate timing analysis due to hard-To-predict access patterns, with few works dealing with time analyzability of multi-level cache hierarchies. For measurement-based timing analysis (MBTA) techniques-widely used in domains such as avionics, automotive, and rail-we propose several cache hierarchies amenable to MBTA. We focus on a probabilistic variant of MBTA (or MBPTA) that requires caches with time-randomized behavior whose execution time variability can be captured in the measurements taken during system's test runs. For this type of caches, we explore and propose different multi-level cache setups. From those, we choose a cost-effective cache hierarchy that we implement and integrate in a 4-core LEON3 RTL processor model and prototype in a FPGA. Our results show that our proposed setup implemented in RTL results in better (reduced) WCET estimates with similar implementation cost and no impact on average performance w.r.t. other MBPTA-Amenable setups.
CitationBenedicte, P., Hernandez, C., Abella, J., Cazorla, F. J. Design and integration of hierarchical-placement multi-level caches for real-Time systems. A: Design, Automation and Test in Europe Conference and Exhibition. "2018 Design, Automation & Test in Europe Conference & Exhibition (DATE 2018): Dresden, Germany; 19-23 March 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 455-460.
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