Exploració per autor "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 1-20 de 143
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A cache design for probabilistically analysable real-time systems
Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
Text en actes de congrés
Accés restringit per política de l'editorialCaches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ... -
A confidence assessment of WCET estimates for software time randomized caches
Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertObtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ... -
A cross-layer review of deep learning frameworks to ease their optimization and reuse
Tabani, Hamid; Pujol Torramorell, Roger; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertMachine learning and especially Deep Learning (DL) approaches are at the heart of many domains, from computer vision and speech processing to predicting trajectories in autonomous driving and data science. Those approaches ... -
A methodology for selective protection of matrix multiplications: A diagnostic coverage and performance trade-off for CNNs executed on GPUs
Fernández Muñoz, Javier; Agirre Troncoso, Irune; Pérez Cerrolaza, Jon; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe ability of CNNs to efficiently and accurately perform complex functions, such as object detection, has fostered their adoption in safety-related autonomous systems. These algorithms require high computational performance ... -
A Methodology for Selective Protection of Matrix Multiplications: A Diagnostic Coverage and Performance Trade-off for CNNs Executed on GPUs
Fernández, Javier; Agirre, Irune; Perez Cerrolaza, Jon; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThe ability of CNNs to efficiently and accurately perform complex functions, such as object detection, has fostered their adoption in safety-related autonomous systems. These algorithms require high computational performance ... -
A software-only approach to enable diverse redundancy on Intel GPUs for safety-related kernels
Andriotis, Nikolaos; Serrano Cases, Alejandro; Alcaide Portet, Sergi; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier; Peng, Yang; Baldovin, Andrea; Paulitsch, Michael; Tsymbal, Vladimir (Association for Computing Machinery (ACM), 2023)
Text en actes de congrés
Accés obertAutonomous Driving (AD) systems rely on object detection and tracking algorithms that require processing high volumes of data at high frequency. High-performance graphics processing units (GPUs) have been shown to provide ... -
Accurately measuring contention in Mesh NoCs in time-sensitive embedded systems
Cardona Nadal, Jordi; Hernández Luz, Carles; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023-05)
Article
Accés obertThe computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous ... -
Achieving timing composability with measurement-based probabilistic timing analysis
Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ... -
ADBench: benchmarking autonomous driving systems
Tabani, Hamid; Pujol Torramorell, Roger; Alcón Doganoc, Miguel; Moya Riera, Joan; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2022)
Article
Accés obertDriven by the improvements in a variety of domains, autonomous driving is becoming a reality and today, industry aims at moving toward fully autonomous vehicles. High-tech chip manufacturers are designing high-performance ... -
An academic RISC-V silicon implementation based on open-source components
Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An analyzable memory controller for hard real-time CMPs
Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
Article
Accés obertMulticore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ... -
An approach for detecting power peaks during testing and breaking systematic pathological behavior
Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThe verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ... -
An automotive case study on the limits of approximation for object detection
Caro Roca, Martí; Tabani, Hamid; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Morancho Llena, Enrique; Canal Corretger, Ramon; Altet Sanahujes, Josep; Calomarde Palomino, Antonio; Cazorla Almeida, Francisco Javier; Rubio Romano, Antonio; Fontova Muste, Pau; Fornt Mas, Jordi (2023-05)
Article
Accés restringit per política de l'editorialThe accuracy of camera-based object detection (CBOD) built upon deep learning is often evaluated against the real objects in frames only. However, such simplistic evaluation ignores the fact that many unimportant objects ... -
An on-board algorithm implementation on an embedded GPU: A space case study
Rodríguez Ferrandez, Iván; Kosmidis, Leonidas; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertOn-board processing requirements of future space missions are constantly increasing, calling for new hardware than the traditional ones used in space. Embedded GPUs are an attractive candidate offering both high performance ... -
Applying measurement-based probabilistic timing analysis to buffer resources
Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
Text en actes de congrés
Accés obertThe use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ... -
Architectural support for real-time task scheduling in SMT processors
Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernández, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
Report de recerca
Accés obertIn Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ... -
ASCOM: Affordable Sequence-aware COntention Modeling in crossbar-based MPSoCs
Giesen León, Jeremy Jens; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023)
Comunicació de congrés
Accés obertMulticore interference that arises when several accesses contend for the same shared hardware resources poses a challenge to the already demanding consolidated verification and validation practice. The Sequence-Aware Pairing ... -
Bus designs for time-probabilistic multicore processors
Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ... -
Cache side-channel attacks and time-predictability in high-performance critical real-time systems
Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
Comunicació de congrés
Accés obertEmbedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ... -
Characterizing the resource-sharing levels of the UltraSparc T2 processor
Cakarevic, Vladimir; Radojković, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
Text en actes de congrés
Accés restringit per política de l'editorialThread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...