Now showing items 1-20 of 104

    • A cache design for probabilistically analysable real-time systems 

      Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
      Conference report
      Restricted access - publisher's policy
      Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ...
    • A confidence assessment of WCET estimates for software time randomized caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...
    • A cross-layer review of deep learning frameworks to ease their optimization and reuse 

      Tabani, Hamid; Pujol Torramorell, Roger; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Machine learning and especially Deep Learning (DL) approaches are at the heart of many domains, from computer vision and speech processing to predicting trajectories in autonomous driving and data science. Those approaches ...
    • Achieving timing composability with measurement-based probabilistic timing analysis 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (2013)
      Conference report
      Restricted access - publisher's policy
      Probabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalabros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moreto Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
    • An analyzable memory controller for hard real-time CMPs 

      Paolieri, Marco; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier; Valero Cortés, Mateo (2010-02-05)
      Article
      Open Access
      Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ...
    • An approach for detecting power peaks during testing and breaking systematic pathological behavior 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ...
    • An on-board algorithm implementation on an embedded GPU: A space case study 

      Rodríguez Ferrandez, Iván; Kosmidis, Leonidas; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      On-board processing requirements of future space missions are constantly increasing, calling for new hardware than the traditional ones used in space. Embedded GPUs are an attractive candidate offering both high performance ...
    • Applying measurement-based probabilistic timing analysis to buffer resources 

      Kosmidis, Leonidas; Vardanega, Tulio; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2013)
      Conference report
      Open Access
      The use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ...
    • Architectural support for real-time task scheduling in SMT processors 

      Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernández, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2005)
      External research report
      Open Access
      In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ...
    • Bus designs for time-probabilistic multicore processors 

      Jalle Ibarra, Javier; Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Conference report
      Restricted access - publisher's policy
      Probabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ...
    • Cache side-channel attacks and time-predictability in high-performance critical real-time systems 

      Trilla Rodríguez, David; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06-24)
      Conference lecture
      Open Access
      Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ...
    • Characterizing the resource-sharing levels of the UltraSparc T2 processor 

      Cakarevic, Vladimir; Radojkovic, Petar; Verdú Mulà, Javier; Pajuelo González, Manuel Alejandro; Cazorla Almeida, Francisco Javier; Nemirovsky, Mario; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2009)
      Conference report
      Restricted access - publisher's policy
      Thread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ...
    • CleanET: enabling timing validation for complex automotive systems 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Tabani, Hamid; Abella Ferrer, Jaume; del Castillo Franquet, Joan; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020)
      Conference report
      Open Access
      Timing validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ...
    • Containing timing-related certification cost in automotive systems deploying complex hardware 

      Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Farrall, Glenn; Wartel, Franck; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2014)
      Conference report
      Restricted access - publisher's policy
      Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ...
    • Contention in multicore hardware shared resources: Understanding of the state of the art 

      Fernández, Gabriel; Abella Ferrer, Jaume; Quiñones, Eduardo; Rochange, Christine; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
      Conference report
      Open Access
      The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ...
    • Contention-aware performance monitoring counter support for real-time MPSoCs 

      Jalle Ibarra, Javier; Fernández, Mikel; Abella Ferrer, Jaume; Andersson, Jan; Patte, Mathieu; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference lecture
      Open Access
      Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ...
    • Data bus slicing for contention-free multicore real-time memory systems 

      Jalle Ibarra, Javier; Quiñones, Eduardo; Abella Ferrer, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Memory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ...
    • Dcache Warn: an I-fetch policy to increase SMT efficiency 

      Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Garcia, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
      Conference report
      Open Access
      Simultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ...
    • Deconstructing bus access control policies for real-time multicores 

      Jalle Ibarra, Javier; Abella Ferrer, Jaume; Quiñones, Eduardo; Fossati, Luca; Zulianello, Marco; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Conference report
      Restricted access - publisher's policy
      Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...