Browsing by Author "Cazorla Almeida, Francisco Javier"
Now showing items 1-20 of 104
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A cache design for probabilistically analysable real-time systems
(2013)
Conference report
Restricted access - publisher's policyCaches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. ... -
A confidence assessment of WCET estimates for software time randomized caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessObtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ... -
A cross-layer review of deep learning frameworks to ease their optimization and reuse
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessMachine learning and especially Deep Learning (DL) approaches are at the heart of many domains, from computer vision and speech processing to predicting trajectories in autonomous driving and data science. Those approaches ... -
Achieving timing composability with measurement-based probabilistic timing analysis
(2013)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An analyzable memory controller for hard real-time CMPs
(2010-02-05)
Article
Open AccessMulticore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences ... -
An approach for detecting power peaks during testing and breaking systematic pathological behavior
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessThe verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on ... -
An on-board algorithm implementation on an embedded GPU: A space case study
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessOn-board processing requirements of future space missions are constantly increasing, calling for new hardware than the traditional ones used in space. Embedded GPUs are an attractive candidate offering both high performance ... -
Applying measurement-based probabilistic timing analysis to buffer resources
(2013)
Conference report
Open AccessThe use of complex hardware makes it difficult for current timing analysis techniques to compute trustworthy and tight worst-case execution time (WCET) bounds. Those techniques require detailed knowledge of the internal ... -
Architectural support for real-time task scheduling in SMT processors
(2005)
External research report
Open AccessIn Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architectures suitable for use in embedded systems. ... -
Bus designs for time-probabilistic multicore processors
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Restricted access - publisher's policyProbabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design ... -
Cache side-channel attacks and time-predictability in high-performance critical real-time systems
(Association for Computing Machinery (ACM), 2018-06-24)
Conference lecture
Open AccessEmbedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous ... -
Characterizing the resource-sharing levels of the UltraSparc T2 processor
(Association for Computing Machinery (ACM), 2009)
Conference report
Restricted access - publisher's policyThread level parallelism (TLP) has become a popular trend to improve processor performance, overcoming the limitations of extracting instruction level parallelism. Each TLP paradigm, such as Simultaneous Multithreading or ... -
CleanET: enabling timing validation for complex automotive systems
(Association for Computing Machinery (ACM), 2020)
Conference report
Open AccessTiming validation for automotive systems occurs in late integration stages when it is hard to control how the instances of software tasks overlap in time. To make things worse, in complex software systems, like those for ... -
Containing timing-related certification cost in automotive systems deploying complex hardware
(Association for Computing Machinery (ACM), 2014)
Conference report
Restricted access - publisher's policyMeasurement-Based Probabilistic Timing Analysis (MBPTA) techniques simplify deriving tight and trustworthy WCET estimates for industrial-size programs running on complex processors. MBPTA poses some requirements on the ... -
Contention in multicore hardware shared resources: Understanding of the state of the art
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2014)
Conference report
Open AccessThe real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources. The relevance of this problem has been ... -
Contention-aware performance monitoring counter support for real-time MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference lecture
Open AccessTasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task ... -
Data bus slicing for contention-free multicore real-time memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessMemory access contention is one of the main contributors to tasks' execution time variability in real-Time multicores. Existing techniques to control memory contention based on time-sharing memory access do not scale well ... -
Dcache Warn: an I-fetch policy to increase SMT efficiency
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessSimultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, ... -
Deconstructing bus access control policies for real-time multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key ...
