Browsing by Author "Benedicte Illescas, Pedro"
Now showing items 1-20 of 25
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A confidence assessment of WCET estimates for software time randomized caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessObtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ... -
Behavior characterization of the shared last-level cache in a chip multiprocessor
(Universitat Politècnica de Catalunya, 2014-06-27)
Master thesis (pre-Bologna period)
Open Access[CATALÀ] Aquest projecte consisteix a analitzar diferents aspectes de la jerarquia de memòria i entendre la seva influència al rendiment del sistema. Els aspectes que s'analitzaran són els algorismes de reemplaçament, els ... -
De-RISC: A complete RISC-V based space-grade platform
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessThe H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and ... -
Design and integration of hierarchical-placement multi-level caches for real-Time systems
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyEnabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ... -
End-to-end QoS for the open source safety-relevant RISC-V SELENE platform
(arXiv, 2022)
Conference report
Open AccessThis paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ... -
HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
Conference report
Open AccessHigh-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ... -
Improving time-randomized cache design
(Barcelona Supercomputing Center, 2018-04-24)
Conference report
Open AccessEnabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ... -
LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache
(IEEE, 2019-05-16)
Conference lecture
Open AccessAs implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible ... -
Locality-aware cache random replacement policies
(2019-02-01)
Article
Open AccessMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Locality-aware cache random replacement policies
(Elsevier, 2019-02)
Article
Open AccessMeasurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ... -
Modeling contention interference in crossbar-based systems via Sequence-Aware Pairing (SeAP)
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe Infineon AURIX TriCore family of microcontrollers has consolidated as the reference multicore computing platform for safety-critical systems in the automotive domain. As a distinctive trait, AURIX microcontrollers are ... -
Modelling the confidence of timing analysis for time randomised caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Open AccessTiming is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ... -
On the analysis of the timing behaviour of time randomised caches
(Universitat Politècnica de Catalunya, 2016-07-07)
Master thesis
Open AccessTime Randomised caches (TRc), which can be implemented at hardware level or with software means on conventional deterministic cache designs, have been proposed for real-time systems as key enablers for Probabilistic ... -
Performance analysis and optimization of automotive GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessAdvanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) have drastically increased the performance demands of automotive systems. Suitable highperformance platforms building upon Graphic Processing Units ... -
Performance analysis and optimization opportunities for NVIDIA automotive GPUs
(Elsevier, 2021-06)
Article
Open AccessAdvanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) bring unprecedented performance requirements for automotive systems. Graphic Processing Unit (GPU) based platforms have been deployed with the aim of ... -
RPR: a random replacement policy with limited pathological replacements
(Association for Computing Machinery (ACM), 2018)
Conference report
Restricted access - publisher's policyMeasurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ... -
SafeDE: A low-cost hardware solution to enforce diverse redundancy in multicores
(Institute of Electrical and Electronics Engineers (IEEE), 2022-06)
Article
Open AccessFailure risk must be tiny in high-integrity systems, such as those in cars, satellites and aircraft. Hence, safety measures must be deployed to avoid a single fault leading to a failure. Redundancy has been often used to ... -
SafeDM: a hardware diversity monitor for redundant execution on non-lockstepped cores
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessComputing systems in the safety domain, such as those in avionics or space, require specific safety measures related to the criticality of the deployment. A problem these systems face is that of transient failures in ... -
SafeSoftDR: A library to enable software-based diverse redundancy for safety-critical tasks
(arXiv, 2022)
Conference report
Open AccessApplications with safety requirements have become ubiquitous nowadays and can be found in edge devices of all kinds. However, microcontrollers in those devices, despite offering moderate performance by implementing multicores ... -
SafeSU-2: a safe statistics unit for space MPSoCs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessAdvanced statistics units (SUs) have been proven effective for the verification, validation and implementation of safety measures as part of safety-related MPSoCs. This is the case, for instance, of the RISC-V MPSoC by ...
