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dc.contributor.authorAsifuzzaman, Kazi
dc.contributor.authorPavlovic, Milan
dc.contributor.authorRadulović, Milan
dc.contributor.authorZaragoza, David
dc.contributor.authorKwon, Ohseong
dc.contributor.authorRyoo, Kyung-Chang
dc.contributor.authorRadojkovic, Petar
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2016-10-26T09:27:13Z
dc.date.available2016-10-26T09:27:13Z
dc.date.issued2016-10
dc.identifier.citationAsifuzzaman, Kazi [et al.]. Performance impact of a slower main memory: a case study of STT-MRAM in HPC. A: MEMSYS '16. "Proceedings of the Second International Symposium on Memory Systems". ACM, 2016, p. 40-49.
dc.identifier.isbn978-1-4503-4305-3
dc.identifier.urihttp://hdl.handle.net/2117/91091
dc.description.abstractIn high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.
dc.description.sponsorshipThis work was supported by the Collaboration Agreement between Samsung Electronics Co., Ltd. and BSC, Spanish Government through Programa Severo Ochoa (SEV-2015-0493), by the Spanish Ministry of Science and Technology through TIN2015-65316-P project and by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272). This work has also received funding from the European Union's Horizon 2020 research and innovation programme under ExaNoDe project (grant agreement No 671578).
dc.format.extent10 p.
dc.language.isoeng
dc.publisherACM
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshProcessors, High performance
dc.subject.lcshSupercomputers--Programming
dc.subject.lcshMemory--Computer simulation
dc.subject.otherProcessors and memory architectures
dc.subject.otherNon-volatile memory
dc.subject.otherMassively parallel and high-performance simulations
dc.subject.otherSTT-MRAM
dc.subject.otherMain memory
dc.subject.otherHigh-performance computing
dc.titlePerformance impact of a slower main memory: a case study of STT-MRAM in HPC
dc.typeConference lecture
dc.subject.lemacOrdinadors--Dispositius de memòria
dc.subject.lemacSupercomputadors
dc.identifier.doi10.1145/2989081.2989082
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671578/EU/European Exascale Processor Memory Node Design/ExaNoDe
local.citation.contributorMEMSYS '16
local.citation.publicationNameProceedings of the Second International Symposium on Memory Systems
local.citation.startingPage40
local.citation.endingPage49


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