Performance impact of a slower main memory: a case study of STT-MRAM in HPC
Document typeConference lecture
Rights accessOpen Access
European Commission's projectExaNoDe - European Exascale Processor Memory Node Design (EC-H2020-671578)
In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) --- byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.
CitationAsifuzzaman, Kazi [et al.]. Performance impact of a slower main memory: a case study of STT-MRAM in HPC. A: MEMSYS '16. "Proceedings of the Second International Symposium on Memory Systems". ACM, 2016, p. 40-49.
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