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dc.contributor.authorGarcía, Marina
dc.contributor.authorVallejo, Enrique
dc.contributor.authorBeivide Palacio, Julio Ramón
dc.contributor.authorOdriozola, Miguel
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2016-10-10T07:53:22Z
dc.date.available2016-10-10T07:53:22Z
dc.date.issued2013
dc.identifier.citationGarcía, M., Vallejo, E., Beivide, R., Odriozola, M., Valero, M. Efficient routing mechanisms for Dragonfly networks. A: International Conference on Parallel Processing. "International Conference on Parallel Processing: the 42nd Annual Conference, ICPP 2013: 1-4 October 2013, Lyon, France". Lyon: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 582-592.
dc.identifier.isbn978-0-7695-5117-3
dc.identifier.urihttp://hdl.handle.net/2117/90617
dc.description.abstractHigh-radix hierarchical networks are cost-effective topologies for large scale computers. In such networks, routers are organized in super nodes, with local and global interconnections. These networks, known as Dragonflies, outperform traditional topologies such as multi-trees or tori, in cost and scalability. However, depending on the traffic pattern, network congestion can lead to degraded performance. Misrouting (non-minimal routing) can be employed to avoid saturated global or local links. Nevertheless, with the current deadlock avoidance mechanisms used for these networks, supporting misrouting implies routers with a larger number of virtual channels. This exacerbates the buffer memory requirements that constitute one of the main constraints in high-radix switches. In this paper we introduce two novel deadlock-free routing mechanisms for Dragonfly networks that support on-the-fly adaptive routing. Using these schemes both global and local misrouting are allowed employing the same number of virtual channels as in previous proposals. Opportunistic Local Misrouting obtains the best performance by providing the highest routing freedom, and relying on a deadlock-free escape path to the destination for every packet. However, it requires Virtual Cut-Through flow-control. By contrast, Restricted Local Misrouting prevents the appearance of cycles thanks to a restriction of the possible routes within super nodes. This makes this mechanism suitable for both Virtual Cut-Through and Wormhole networks. Evaluations show that the proposed deadlock-free routing mechanisms prevent the most frequent pathological issues of Dragonfly networks. As a result, they provide higher performance than previous schemes, while requiring the same area devoted to router buffers.
dc.description.sponsorshipThis work has been supported by the Spanish Ministry of Science under contracts TIN2010-21291-C02-02, TIN2012-34557, and by the European HiPEAC Network of Excellence. The research leading to these results has received funding from the European Research Council under the European Union’s Seventh Framework Programme (FP/2007-2013) / ERC Grant Agreement n. ERC-2012-Adg-321253-RoMoL. M. Garc´ıa and M. Odriozola participated in this research work while they were affiliated with the University of Cantabria.
dc.format.extent11 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshRouting (Computer network management)
dc.subject.lcshTelecommunication -- Traffic -- Management
dc.subject.otherDeadlock avoidance
dc.subject.otherDragonfly networks
dc.subject.otherRouting
dc.subject.otherSystem recovery
dc.subject.otherPorts (Computers)
dc.subject.otherTopology
dc.subject.otherNetwork topology
dc.subject.otherProposals
dc.subject.otherAdaptive systems
dc.titleEfficient routing mechanisms for Dragonfly networks
dc.typeConference lecture
dc.subject.lemacEncaminadors (Xarxes d'ordinadors)
dc.subject.lemacTelecomunicació -- Tràfic -- Gestió
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ICPP.2013.72
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/6687396/
dc.rights.accessOpen Access
local.identifier.drac18819529
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
local.citation.authorGarcía, M.; Vallejo, E.; Beivide, R.; Odriozola, M.; Valero, M.
local.citation.contributorInternational Conference on Parallel Processing
local.citation.pubplaceLyon
local.citation.publicationNameInternational Conference on Parallel Processing: the 42nd Annual Conference, ICPP 2013: 1-4 October 2013, Lyon, France
local.citation.startingPage582
local.citation.endingPage592


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