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dc.contributor.authorMunera, Adrian
dc.contributor.authorRoyuela Alcázar, Sara
dc.contributor.authorQuiñones, Eduardo
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2020-06-25T16:15:47Z
dc.date.available2020-06-25T16:15:47Z
dc.date.issued2020
dc.identifier.citationMunera, A.; Royuela Alcázar, S.; Quiñones, E. Towards a qualifiable openMP framework for embedded systems. A: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). "2020 Design, Automation & Test in Europe Conference & Exhibition (DATE): Grenoble, France, 9-13 March 2020: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 903-908.
dc.identifier.isbn978-3-9819263-4-7
dc.identifier.issn1558-1101
dc.identifier.urihttp://hdl.handle.net/2117/191570
dc.description.abstractOpenMP is a very convenient programming model for critical real-time parallel applications due to its powerful tasking model and its proven time predictability. However, current implementations are not suitable for critical environments based on the intensive use of dynamically allocated memory needed to efficiently manage the parallel execution. This jeopardizes the qualification processes needed to ensure that the integrated software stack is compliant with system requirements.This paper proposes a novel OpenMP framework that statically allocates the data structures needed to efficiently manage the parallel execution of OpenMP tasks. Our framework is composed of a compiler that captures the environment of the OpenMP tasks instantiated along the parallel execution and bounds the exposed parallelism, and a runtime implementing a lazy task creation policy that significantly reduces the runtime memory requirements, whilst exploiting parallelism efficiently. The evaluation shows that our tool achieves the same performance as current OpenMP implementations, while bounds and drastically reduces the dynamic memory requirements at run-time.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshHigh performance computing
dc.subject.otherOpenMP
dc.subject.otherMemory allocation
dc.subject.otherQualification
dc.subject.otherEmbedded systems
dc.subject.otherParallel execution
dc.titleTowards a qualifiable openMP framework for embedded systems
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacOpenMP (Interfície de programació d'aplicacions)
dc.identifier.doi10.23919/DATE48585.2020.9116230
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9116230
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
local.citation.contributor2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
local.citation.publicationName2020 Design, Automation & Test in Europe Conference & Exhibition (DATE): Grenoble, France, 9-13 March 2020: proceedings
local.citation.startingPage903
local.citation.endingPage908


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