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Towards a qualifiable openMP framework for embedded systems

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10.23919/DATE48585.2020.9116230
 
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hdl:2117/191570

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Munera, Adrian
Royuela Alcázar, SaraMés informació
Quiñones, Eduardo
Document typeConference report
Defense date2020
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
Abstract
OpenMP is a very convenient programming model for critical real-time parallel applications due to its powerful tasking model and its proven time predictability. However, current implementations are not suitable for critical environments based on the intensive use of dynamically allocated memory needed to efficiently manage the parallel execution. This jeopardizes the qualification processes needed to ensure that the integrated software stack is compliant with system requirements.This paper proposes a novel OpenMP framework that statically allocates the data structures needed to efficiently manage the parallel execution of OpenMP tasks. Our framework is composed of a compiler that captures the environment of the OpenMP tasks instantiated along the parallel execution and bounds the exposed parallelism, and a runtime implementing a lazy task creation policy that significantly reduces the runtime memory requirements, whilst exploiting parallelism efficiently. The evaluation shows that our tool achieves the same performance as current OpenMP implementations, while bounds and drastically reduces the dynamic memory requirements at run-time.
CitationMunera, A.; Royuela Alcázar, S.; Quiñones, E. Towards a qualifiable openMP framework for embedded systems. A: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). "2020 Design, Automation & Test in Europe Conference & Exhibition (DATE): Grenoble, France, 9-13 March 2020: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 903-908. 
URIhttp://hdl.handle.net/2117/191570
DOI10.23919/DATE48585.2020.9116230
ISBN978-3-9819263-4-7
ISSN1558-1101
Publisher versionhttps://ieeexplore.ieee.org/document/9116230
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