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On the resilience of deep learning for reduced-voltage FPGAs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
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Deep Neural Networks (DNNs) are inherently computation-intensive and also power-hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a promising solution that can satisfy these requirements for ...
Towards zero-waste recovery and zero-overhead checkpointing in ensemble data assimilation
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
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Ensemble data assimilation is a powerful tool for increasing the accuracy of climatological states. It is based on combining observations with the results from numerical model simulations. The method comprises two steps, ...
A RISC-V simulator and benchmark suite for designing and evaluating vector architectures
(2020-11)
Article.
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Article.
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Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that ...
Adaptable register file organization for vector processors
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
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Contemporary Vector Processors (VPs) are de-signed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector support, or long vectors, e.g., NEC Aurora Tsubasa with 16Kbits Maximum Vector Length ...
Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
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Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage ...
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge
(Association for Computing Machinery (ACM), 2022)
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Linear algebra computational kernels based on byte and sub-byte integer data formats are at the base of many classes of applications, ranging from Deep Learning to Pattern Matching. Porting the computation of these ...
A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
(IEEE, 2018-12-06)
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Comunicació de congrés.
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The power consumption of digital circuits, e.g., Field Programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage ...
MoRS: An approximate fault modelling framework for reduced-voltage SRAMs
(2022-06)
Article.
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Article.
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On-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g, GPUs, FPGAs, ASICs to achieve high performance. Modern workloads such as Deep ...
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
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Text en actes de congrés.
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We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field ...
Exceeding conservative limits: A consolidated analysis on modern hardware margins
(2020-06)
Article.
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Article.
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Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core ...