Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults
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Cita com:
hdl:2117/188788
Tipus de documentText en actes de congrés
Data publicació2019
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
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Abstract
Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage level and without accompanying frequency scaling leads to timing related faults, potentially undermining the energy savings. Through experimental voltage underscaling studies on commercial FPGAs, we observed that the rate of these faults exponentially increases for on-chip memories, or Block RAMs (BRAMs). To mitigate these faults, we evaluated the efficiency of the built-in Error-Correction Code (ECC) and observed that more than 90 % of the faults are correctable and further 7 % are detectable (but not correctable). This efficiency is the result of the single-bit type of these faults, which are then effectively covered by the Single-Error Correction and Double-Error Detection (SECDED) design of the built-in ECC. Finally, motivated by the above experimental observations, we evaluated an FPGA-based Neural Network (NN) accelerator under low-voltage operations, while built-in ECC is leveraged to mitigate undervolting faults and thus, prevent NN significant accuracy loss. In consequence, we achieve 40 % of the BRAM power saving through undervolting below the minimum safe voltage level, with a negligible NN accuracy loss, thanks to the substantial fault coverage by the built-in ECC.
CitacióSalami, B.; Unsal, O.; Cristal, A. Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2019: Pavia, Italy 13-15 February 2019: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 242-246.
ISBN978-1-7281-1644-0
Versió de l'editorhttps://ieeexplore.ieee.org/document/8671543/
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- Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [285]
- Computer Sciences - Ponències/Comunicacions de congressos [565]
- CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos [784]
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.948]
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