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An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration

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10.1109/DSN48063.2020.00032
 
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Salami, Behzad
Onural, Erhan Baturay
Yuksel, Ismail Emir
Koc, Fahrettin
Ergin, Oguz
Cristal Kestelman, AdriánMés informacióMés informacióMés informació
Unsal, Osman Sabri
Sarbazi-Azad, Hamid
Mutlu, Onur
Document typeConference report
Defense date2020
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder
ProjectHiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-779656)
LEGaTO - Low Energy Toolset for Heterogeneous Computing (EC-H2020-780681)
Abstract
We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect ofenvironmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.
CitationSalami, B. [et al.]. An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration. A: Annual IEEE/IFIP International Conference on Dependable Systems and Networks. "50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks: 29 June-2 July 2020, Valencia, Spain: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2020, p. 138-149. ISBN 978-1-7281-5809-9. DOI 10.1109/DSN48063.2020.00032. 
URIhttp://hdl.handle.net/2117/330567
DOI10.1109/DSN48063.2020.00032
ISBN978-1-7281-5809-9
Publisher versionhttps://ieeexplore.ieee.org/document/9153393
Other identifiershttps://arxiv.org/abs/2005.03451
Collections
  • Doctorat en Arquitectura de Computadors - Ponències/Comunicacions de congressos [196]
  • Computer Sciences - Ponències/Comunicacions de congressos [459]
  • CAP - Grup de Computació d'Altes Prestacions - Ponències/Comunicacions de congressos [762]
  • Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos [1.773]
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