Mostra el registre d'ítem simple

dc.contributor.authorSemenov, Alex
dc.contributor.authorYakovlev, Alex
dc.contributor.authorPastor Llorens, Enric
dc.contributor.authorPeña Basurto, Marco Antonio
dc.contributor.authorCortadella, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.date.accessioned2019-03-12T10:18:15Z
dc.date.available2019-03-12T10:18:15Z
dc.date.issued1997
dc.identifier.citationSemenov, A. [et al.]. Synthesis of speed-independent circuits from STG-unfolding segment. A: Design Automation Conference. "Design Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 16-21.
dc.identifier.isbn0-7803-4093-0
dc.identifier.urihttp://hdl.handle.net/2117/130227
dc.description.abstractThis paper presents a novel technique for synthesis of speed-independent circuits. It is based on partial order representation of the state graph called STG-unfolding segment. The new method uses approximation technique to speed up the synthesis process. The method is illustrated on the basic implementation architecture. Experimental results demonstrating its efficiency are presented and discussed.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshLogic design
dc.subject.lcshLogic circuits
dc.subject.otherCircuit synthesis
dc.subject.otherSignal synthesis
dc.subject.otherPermission
dc.subject.otherData structures
dc.subject.otherBoolean functions
dc.subject.otherConcurrent computing
dc.subject.otherLogic
dc.subject.otherExplosions
dc.subject.otherSamarium
dc.subject.otherCollaborative work
dc.titleSynthesis of speed-independent circuits from STG-unfolding segment
dc.typeConference report
dc.subject.lemacEstructura lògica
dc.subject.lemacCircuits lògics
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/DAC.1997.597110
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/597110
dc.rights.accessOpen Access
local.identifier.drac2377011
dc.description.versionPostprint (published version)
local.citation.authorSemenov, A.; Yakovlev, A.; Pastor, E.; Peña, M.; Cortadella, J.
local.citation.contributorDesign Automation Conference
local.citation.publicationNameDesign Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997
local.citation.startingPage16
local.citation.endingPage21


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple