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  • The octahedron abstract domain 

    Clarisó Viladrosa, Robert; Cortadella, Jordi (Springer, 2004)
    Texto en actas de congreso
    Acceso abierto
    An interesting area in static analysis is the study of numeric properties. Complex properties can be analyzed using abstract interpretation, provided that an adequate abstract domain is defined. Each domain can represent ...

  • A case study for the verification of complex timed circuits: IPCMOS 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Texto en actas de congreso
    Acceso abierto
    The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...

  • Logic design of asynchronous circuits 

    Cortadella, Jordi; Yakovlev, Alex; Garside, Jim (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Texto en actas de congreso
    Acceso abierto
    Summary form only given. This tutorial aims at motivating the audience to consider asynchronous circuits as a competitive alternative to solve some of the design problems inherent to submicron technologies. One of the main ...

  • Formal verification of safety properties in timed circuits 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Kondratyev, Alex; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Texto en actas de congreso
    Acceso abierto
    The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ...

  • A radix-16 SRT division unit with speculation of the quotient digits 

    Gianluca, Cornetta; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Texto en actas de congreso
    Acceso abierto
    The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ...

  • Behavioral transformations to increase the noise immunity of asynchronous specifications 

    Taubin, Alexander; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Texto en actas de congreso
    Acceso abierto
    Noise immunity is becoming one of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problems originated by simultaneous switching ...

  • Combining structural and symbolic methods for the verification of concurrent systems 

    Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Texto en actas de congreso
    Acceso abierto
    The contributions during the last few years on the structural theory of Petri nets can now be applied to formal verification. The structural theory provides methods to find efficient encoding schemes for symbolic representations ...

  • Structural methods to improve the symbolic analysis of Petri nets 

    Pastor Llorens, Enric; Cortadella, Jordi; Peña Basurto, Marco Antonio (Springer, 1999)
    Texto en actas de congreso
    Acceso abierto
    Symbolic techniques based on BDDs (Binary Decision Diagrams) have emerged as an efficient strategy for the analysis of Petri nets. The existing techniques for the symbolic encoding of each marking use a fixed set of variables ...

  • Synthesis of asynchronous control circuits with automatically generated relative timing assumptions 

    Cortadella, Jordi; Kishinevsky, Michael; Burns, Steven M.; Stevens, Kenneth S. (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Texto en actas de congreso
    Acceso abierto
    This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ensure functionality. Relative timing assumptions ...

  • What is the cost of delay insensitivity? 

    Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Texto en actas de congreso
    Acceso abierto
    Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour ...

  • Automatic synthesis and optimization of partially specified asynchronous systems 

    Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Lavagno, Luciano; Yakovlev, Alex (Association for Computing Machinery (ACM), 1999)
    Texto en actas de congreso
    Acceso abierto
    A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key ...

  • CAD directions for high performance asynchronous circuits 

    Stevens, Kenneth S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (Association for Computing Machinery (ACM), 1999)
    Texto en actas de congreso
    Acceso abierto
    This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 ...

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