Recent Submissions

  • Automating synthesis of asynchronous communication mechanisms 

    Cortadella, Jordi; Costa Gorgônio, Kyller; Xia, Fei; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed processes in digital systems. In previous work, systematic ACM synthesis methods have been ...
  • Time-constrained loop pipelining 

    Sánchez Carracedo, Fermín; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on ...
  • Asynchronous multipliers with variable-delay counters 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...
  • A structural encoding technique for the synthesis of asynchronous circuits 

    Carmona Vargas, Josep; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...
  • Physical-aware link allocation and route assignment for chip multiprocessing 

    Nikitin, Nikita; Chatterjee, Satrajit; Cortadella, Jordi; Kishinevsky, Michael; Ogras, Umit (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Open Access
    The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ...
  • A multi-radix approach to asynchronous division 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ...
  • Narrowing the margins with elastic clocks 

    Cortadella, Jordi; Lavagno, Luciano; Amiri, Djavad; Casanova Bachs, Jonàs; Macián, Carlos; Martorell, Ferran; Moya, Juan A.; Necchi, Luca; Sokolov, Danil; Tuncer, Emre (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Open Access
    The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate ...
  • Hardware synthesis for asynchronous communications mechanisms 

    Costa Gorgônio, Kyller; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In this work an automatic method for synthesis of re-reading ACMs is ...
  • Visual semantic re-ranker for text spotting 

    Sabir, Ahmed; Moreno-Noguer, Francesc; Padró, Lluís (2018)
    Conference report
    Open Access
    Many current state-of-the-art methods for text recognition are based on purely local information and ignore the semantic corre- lation between text and its surrounding visual context. In this paper, we propose a post-processing ...
  • Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis 

    Saito, Hiroshi; Kondratyev, Alex; Cortadella, Jordi; Lavagno, Luciano; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Two trends are of major concern for digital circuit designers: the relative increase of interconnect delays with respect to gate delays and the demand for design reuse. Both pose difficult problems to synchronous design ...
  • Verification of timed circuits with symbolic delays 

    Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    Verifying timed circuits is a complex problem even when the delays of the system are fixed. This paper deals with a more challenging problem, the formal verification of timed circuits with unspecified delays represented ...
  • A general model for performance optimization of sequential systems 

    Bufistov, Dmitry; Cortadella, Jordi; Kishinevsky, Michael; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    Retiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already ...

View more