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Recent Submissions
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Exact and heuristic allocation of multi-kernel applications to multi-FPGA platforms
Conference report
Open AccessFPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. However, single FPGA designs may not achieve sufficient task parallelism. In this work, we optimize the mapping of high-performance ... -
Sesquickselect: One and a half pivots for cache-efficient selection
(Curran, 2019)
Conference report
Open AccessBecause of unmatched improvements in CPU performance, memory transfers have become a bottleneck of program execution. As discovered in recent years, this also affects sorting in internal memory. Since partitioning around ... -
Genet: a tool for the synthesis and mining of Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 2009)
Conference report
Open AccessState-based representations of concurrent systems suffer from the well known state explosion problem. In contrast, Petri nets are good models for this type of systems both in terms of complexity of the analysis and in ... -
Lazy transition systems: application to timing optimization of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ... -
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
(Universitat Politècnica de Catalunya (UPC), 1996)
Conference report
Open AccessPetrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ... -
Task generation and compile-time scheduling for mixed data-control embedded software
(Association for Computing Machinery (ACM), 2000)
Conference report
Open AccessThe problem of optimal software synthesis for concurrent processes to be implemented on a single processor is addressed. The approach calls for the representation of the concurrent processes with Petri nets that give a ... -
Verification of asynchronous circuits by BDD-based model checking of Petri nets
(Springer, 1995)
Conference report
Open AccessThis paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification ... -
Exploiting the locality of memory references to reduce the address bus energy
(Association for Computing Machinery (ACM), 1997)
Conference report
Open AccessThe energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. ... -
Synthesis of synchronous elastic architectures
(Association for Computing Machinery (ACM), 2006)
Conference report
Open AccessA simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, ... -
Automating synthesis of asynchronous communication mechanisms
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessAsynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed processes in digital systems. In previous work, systematic ACM synthesis methods have been ... -
Time-constrained loop pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessThis paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on ... -
Asynchronous multipliers with variable-delay counters
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Conference report
Open AccessAlthough multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...
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