Recent Submissions

  • The model judge : a tool for supporting novices in learning process modeling 

    Delicado Alcántara, Luis; Sánchez Ferreres, Josep; Carmona Vargas, Josep; Padró, Lluís (CEUR-WS.org, 2018)
    Conference report
    Open Access
    Process models are a fundamental element in the BPM lifecycle. Hence, it is of paramount importance for organizations to rely on high-quality, accurate and up-to-date process models, to avoid taking decisions on the basis ...
  • Synchronous elastic networks 

    Krstic, Sava; Cortadella, Jordi; Kishinevsky, Michael; O'Leary, John (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Conference report
    Open Access
    We formally define - at the stream transformer level - a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properties of networks of such circuits and prove ...
  • A region-based algorithm for discovering Petri nets from event logs 

    Carmona Vargas, Josep; Cortadella, Jordi; Kishinevsky, Michael (Springer, 2008)
    Conference report
    Open Access
    The paper presents a new method for the synthesis of Petri nets from event logs in the area of Process Mining. The method derives a bounded Petri net that over-approximates the behavior of an event log. The most important ...
  • Verification of concurrent systems with parametric delays using octahedra 

    Clarisó Viladrosa, Robert; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, ...
  • Coping with the variability of combinational logic delays 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper proposes a technique for creating a combinational logic network with an output that signals when all other outputs have stabilized. The method is based on dual-rail encoding, and guarantees low timing overhead ...
  • Correct-by-construction microarchitectural pipelining 

    Kam, Timothy; Kishinevsky, Michael; Cortadella, Jordi; Galcerán Oms, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Conference report
    Open Access
    This paper presents a method for correct-by-construction microarchitectural pipelining that handles cyclic systems with dependencies between iterations. Our method combines previously known bypass and retiming transformations ...
  • A symbolic algorithm for the synthesis of bounded Petri nets 

    Carmona Vargas, Josep; Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Springer, 2008)
    Conference report
    Open Access
    This paper presents an algorithm for the synthesis of bounded Petri nets from transition systems. A bounded Petri net is always provided in case it exists. Otherwise, the events are split into several transitions to guarantee ...
  • Handshake protocols for de-synchronization 

    Blunno, Ivan; Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    De-synchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for de-synchronization and formally proves their correctness. ...
  • From synchronous to asynchronous: an automatic approach 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Lwin, Kelvin; Sotiriou, Christos P. (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method ...
  • Boolean decomposition using two-literal divisors 

    Modi, Nilesh A.; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Conference report
    Open Access
    This paper is an attempt to answer the following question: how much improvement can be obtained in logic decomposition by using Boolean divisors? Traditionally, the existence of too many Boolean divisors has been the main ...
  • Quasi-static scheduling for concurrent architectures 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Watanabe, Yosinori (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Conference report
    Open Access
    We present a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent tasks, while considering multiple concurrent execution ...
  • Input/output compatibility of reactive systems 

    Carmona Vargas, Josep; Cortadella, Jordi (Springer, 2002)
    Conference report
    Open Access
    The notion of I/O compatibility of reactive systems is defined. It models the fact that two systems can be connected and establish a correct dialogue through their input and output events. I/O compatibility covers safeness ...

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