Recent Submissions

  • Genet: a tool for the synthesis and mining of Petri nets 

    Carmona Vargas, Josep; Cortadella, Jordi; Kishinevsky, Michael
    Conference report
    Open Access
    State-based representations of concurrent systems suffer from the well known state explosion problem. In contrast, Petri nets are good models for this type of systems both in terms of complexity of the analysis and in ...
  • Lazy transition systems: application to timing optimization of asynchronous circuits 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Taubin, Alexander; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Conference report
    Open Access
    The paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzTSs can be effectively used to model the ...
  • Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (Universitat Politècnica de Catalunya (UPC), 1996)
    Conference report
    Open Access
    Petrifyis a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition ...
  • Task generation and compile-time scheduling for mixed data-control embedded software 

    Cortadella, Jordi; Kondratyev, Alex; Lavagno, Luciano; Massot, Marc; Moral Boadas, Sandra; Passerone, Claudio; Watanabe, Yosinori; Sangiovanni-Vincentelli, Alberto (Association for Computing Machinery (ACM), 2000)
    Conference report
    Open Access
    The problem of optimal software synthesis for concurrent processes to be implemented on a single processor is addressed. The approach calls for the representation of the concurrent processes with Petri nets that give a ...
  • Verification of asynchronous circuits by BDD-based model checking of Petri nets 

    Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric (Springer, 1995)
    Conference report
    Open Access
    This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification ...
  • Exploiting the locality of memory references to reduce the address bus energy 

    Musoll Cinca, Enric; Lang, Tomás; Cortadella, Jordi (Association for Computing Machinery (ACM), 1997)
    Conference report
    Open Access
    The energy consumption at the I/O pins is a significant part of the overall chip consumption. This paper presents a method for encoding an external address bus which lowers its activity and, thus, decreases the energy. ...
  • Synthesis of synchronous elastic architectures 

    Cortadella, Jordi; Kishinevsky, Michael; Grundmann, Bill (Association for Computing Machinery (ACM), 2006)
    Conference report
    Open Access
    A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, ...
  • Automating synthesis of asynchronous communication mechanisms 

    Cortadella, Jordi; Costa Gorgônio, Kyller; Xia, Fei; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed processes in digital systems. In previous work, systematic ACM synthesis methods have been ...
  • Time-constrained loop pipelining 

    Sánchez Carracedo, Fermín; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
    Conference report
    Open Access
    This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on ...
  • Asynchronous multipliers with variable-delay counters 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...
  • A structural encoding technique for the synthesis of asynchronous circuits 

    Carmona Vargas, Josep; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...
  • Physical-aware link allocation and route assignment for chip multiprocessing 

    Nikitin, Nikita; Chatterjee, Satrajit; Cortadella, Jordi; Kishinevsky, Michael; Ogras, Umit (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Open Access
    The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ...

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