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A fault-tolerant last level cache for CMPs operating at ultra-low voltage

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10.1016/j.jpdc.2018.10.010
 
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Ferrerón, Alexandra
Alastruey, Jesús
Suárez Gracía, Dario
Monreal Arnal, TeresaMés informacióMés informacióMés informació
Ibáñez Marín, Pablo Enrique
Viñals Yúfera, Víctor
Document typeArticle
Defense date2019-03
PublisherElsevier
Rights accessOpen Access
Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain
ProjectCOMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
Abstract
Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent with a hard fault. Block disabling is a micro-architectural technique that allows low-voltage operation by deactivating faulty cache entries, at the expense of reducing the effective cache capacity. In the case of the last-level cache, this capacity reduction leads to an increase in off-chip memory accesses, diminishing the overall energy benefit of reducing the voltage supply. In this work, we exploit the reuse locality and the intrinsic redundancy of multi-level inclusive hierarchies to enhance the performance of block disabling with negligible cost. The proposed fault-aware last-level cache management policy maps critical blocks, those not present in private caches and with a higher probability of being reused, to active cache entries. Our evaluation shows that this fault-aware management results in up to 37.3% and 54.2% fewer misses per kilo instruction (MPKI) than block disabling for multiprogrammed and parallel workloads, respectively. This translates to performance enhancements of up to 13% and 34.6% for multiprogrammed and parallel workloads, respectively.
CitationFerrerón, A. [et al.]. A fault-tolerant last level cache for CMPs operating at ultra-low voltage. "Journal of parallel and distributed computing", Març 2019, vol. 125, p. 31-44. 
URIhttp://hdl.handle.net/2117/127595
DOI10.1016/j.jpdc.2018.10.010
ISSN0743-7315
Publisher versionhttps://www.sciencedirect.com/science/article/pii/S0743731518307810
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  • Departament d'Arquitectura de Computadors - Articles de revista [967]
  • CAP - Grup de Computació d'Altes Prestacions - Articles de revista [380]
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