Enviaments recents

  • EMVS: Embedded Multi Vector-core System 

    Hussain, Tassadaq; Haider, Amna; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard (2018-06)
    Article
    Accés restringit per política de l'editorial
    With the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications. The existing embedded HPC ...
  • Reuse Detector: improving the management of STT-RAM SLLCs 

    Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
    Article
    Accés restringit per política de l'editorial
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...
  • Asynchronous and exact forward recovery for detected errors in iterative solvers 

    Jaulmes, Luc Etienne; Casas, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2018-03-19)
    Article
    Accés obert
    Current trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ...
  • Runtime vs. manual data distribution for architecture-agnostic shared-memory programming models 

    Nikolopoulos, Dimitrios; Ayguadé Parra, Eduard; Polychronopoulos, C D (2002-08)
    Article
    Accés restringit per política de l'editorial
    This paper compares data distribution methodologies for scaling the performance of OpenMP on NUMA architectures. We investigate the performance of automatic page placement algorithms implemented in the operating system, ...
  • Static and dynamic locality optimizations using integer linear programming 

    Kandemir, M; Banerjee, P; Choudhary, A; Ramanujam, J; Ayguadé Parra, Eduard (2001-09)
    Article
    Accés obert
    The delivered performance on modern processors that employ deep memory hierarchies is closely related to the performance of the memory subsystem. Compiler optimizations aimed at improving cache locality are critical in ...
  • Tools and techniques for automatic data layout: a case study 

    Ayguadé Parra, Eduard; García Almiñana, Jordi; Kremer, Ulrich (1998-05)
    Article
    Accés restringit per política de l'editorial
    Parallel architectures with physically distributed memory providing computing cycles and large amounts of memory are becoming more and more common. To make such architectures truly usable, programming models and support ...
  • A general guide to applying machine learning to computer architecture 

    Nemirovsky, Daniel; Arkose, Tugberk; Markovic, Nikola; Nemirovsky, Mario; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018)
    Article
    Accés obert
    The resurgence of machine learning since the late 1990s has been enabled by significant advances in computing performance and the growth of big data. The ability of these algorithms to detect complex patterns in data which ...
  • Reducing cache coherence traffic with a NUMA-aware runtime approach 

    Caheny, Paul; Alvarez, Lluc; Derradji, Said; Valero Cortés, Mateo; Moreto Planas, Miquel; Casas Guix, Marc (2018-05)
    Article
    Accés obert
    Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves ...
  • Vector processing-aware advanced clock-gating techniques for low-power fused multiply-add 

    Ratkovic, Ivan; Palomar Pérez, Óscar; Stanic, Milan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Valero Cortés, Mateo (2018-04-04)
    Article
    Accés obert
    The need for power efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a retailoring for the mobile market ...
  • A proposal to develop and assess professional skills in Engineering Final Year Projects 

    Sánchez Carracedo, Fermín; Climent Vilaró, Joan; Corbalán González, Julita; Fonseca Casas, Pau; García Almiñana, Jordi; Herrero Zaragoza, José Ramón; Rodríguez Hontoria, Horacio; Sancho Samsó, María Ribera (Tempus Publications, 2018-03)
    Article
    Accés restringit per política de l'editorial
    In this paper we discuss the result of piloting a methodology for Engineering Final Year Projects (FYP) assessment that takes into consideration professional skills acquisition. The FYP is structured around three milestones; ...
  • On the behavior of convolutional nets for feature extraction 

    Garcia-Gasulla, Dario; Pares, Ferran; Vilalta, Armand; Moreno, Jonatan; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Cortés García, Claudio Ulises; Suzumura, Toyotaro (2018-03)
    Article
    Accés obert
    Deep neural networks are representation learning techniques. During training, a deep net is capable of generating a descriptive language of unprecedented size and detail in machine learning. Extracting the descriptive ...
  • Las mentiras del EEES 

    Sánchez Carracedo, Fermín (Asociación de Enseñantes Universitarios de la Informática (AENUI), 2018-01)
    Article
    Accés obert
    En este artículo se presenta el punto de vista del autor sobre cómo se han implantado los planes de estudio del EEES en España y algunas de las cosas que, en su opinión, no se han hecho bien. El EEES despertó muchas ...

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