Now showing items 1-20 of 24

  • A comparison of cache hierarchies for SMT processors 

    Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
    Conference report
    Open Access
    In the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such ...
  • A fault-tolerant last level cache for CMPs operating at ultra-low voltage 

    Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (Elsevier, 2019-03)
    Article
    Restricted access - publisher's policy
    Voltage scaling to values near the threshold voltage is a promising technique to hold off the many-core power wall. However, as voltage decreases, some SRAM cells are unable to operate reliably and show a behavior consistent ...
  • An adaptive controller to save dynamic energy in LP-NUCA 

    Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
    Conference report
    Open Access
    Portable devices often demand powerful processors to run computing intensive applications, such as video playing or gaming, and ultra low en-ergy consumption to extend device uptime. Such con-flicting requirements are hard ...
  • Block disabling characterization and improvements in CMPs operating at ultra-low voltages 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Power density has become the limiting factor in technology scaling as power budget restricts the amount of hardware that can be active at the same time. Reducing supply voltage to ultra-low voltage ranges close to the ...
  • Concertina: Squeezing in cache content to operate at near-threshold voltage 

    Ferrerón, Alexandra; Suárez Gracia, Darío; Alastruey, Jesús; Monreal Arnal, Teresa; Ibáñez, Pablo (2016-03-01)
    Article
    Open Access
    Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, ...
  • Delaying physical register allocation trought virtual-physical registers 

    Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
  • Examen Final 

    Gil Martín, Marçal; Jordán Fernández, Francisco; Monreal Arnal, Teresa; Otero Calviño, Beatriz (Universitat Politècnica de Catalunya, 2015-06-15)
    Exam
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  • Examen Final 

    Heredero Lazaro, Ana M.; Jiménez Castells, Marta; Llorente Viejo, Silvia; Macías Lloret, Mario; Monreal Arnal, Teresa; Pérez Rico, José Luis; Otero Calviño, Beatriz; Valverde Amador, Antonio Javier; Guerrero Zapata, Josep Maria; Gil, Marisa (Universitat Politècnica de Catalunya, 2013-01-18)
    Exam
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  • Examen Final 

    Gil Martín, Marçal; Heredia, F.-Javier (Francisco Javier); Jiménez, M.; Macías Lloret, Mario; Monreal Arnal, Teresa; Pérez, J.L.; Otero Calviño, Beatriz; Valverde Amador, Antonio Javier (Universitat Politècnica de Catalunya, 2013-06-26)
    Exam
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  • Examen Final 

    Gil Martín, Marçal; Guerrero, M.; Jiménez, M.; Jordán Fernández, Francisco; Llorente Viejo, Silvia; Macias, M.; Monreal Arnal, Teresa; Otero Calviño, Beatriz; Valverde Amador, Antonio Javier (Universitat Politècnica de Catalunya, 2014-01-07)
    Exam
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  • Examen Final 

    Valverde Amador, Antonio Javier; Otero Calviño, Beatriz; Monreal Arnal, Teresa; Jordán Fernández, Francisco; Gil Martín, Marçal (Universitat Politècnica de Catalunya, 2014-06-06)
    Exam
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  • Examen Final 

    Macías Lloret, Mario; Jordán Fernández, Francisco; Jiménez, M; Guerrero, M.; Gil Martín, Marçal; Monreal Arnal, Teresa (Universitat Politècnica de Catalunya, 2015-01-09)
    Exam
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  • Gestión de contenidos en caches operando a bajo voltaje 

    Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (2016)
    Conference report
    Open Access
    La eficiencia energética de las caches en chip puede mejorarse reduciendo su voltaje de alimentación (Vdd ). Sin embargo, este escalado de Vdd está limitado a una tensión Vddmin por debajo de la cual algunas celdas SRAM ...
  • Hardware schemes for early register release 

    Monreal Arnal, Teresa; Viñals Yufera, Víctor; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is quite related to the ...
  • Late allocation and early release of physical registers 

    Monreal Arnal, Teresa; Viñals Yufera, Víctor; González González, José; González Colás, Antonio María; Valero Cortés, Mateo (2004-10)
    Article
    Open Access
    The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ...
  • Light NUCA: a proposal for bridging the inter-cache latency gap 

    Suárez, Dario; Monreal Arnal, Teresa; Vallejo, Fernando; Beivide Palacio, Julio Ramón; Viñals Yufera, Víctor (IEEE Computer Society, 2009)
    Conference lecture
    Open Access
    To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). ...
  • Microarchitectural support for speculative register renaming 

    Alastruey, Jesús; Monreal Arnal, Teresa; Viñals Yufera, Víctor; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    This paper proposes and evaluates a new microarchitecture for out-of-order processors that supports speculative renaming. We call speculative renaming to the speculative omission of physical register allocation along with ...
  • ReD: A policy based on reuse detection for demanding block selection in last-level Caches 

    Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
    Conference report
    Open Access
    In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ...
  • ReD: A reuse detector for content selection in exclusive shared last-level caches 

    Díaz, Javier; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Llaberia Griñó, José M.; Viñals Yúfera, Víctor (Elsevier, 2019-03)
    Article
    Restricted access - publisher's policy
    The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ...
  • Reuse Detector: improving the management of STT-RAM SLLCs 

    Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
    Article
    Open Access
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...