Enviaments recents

  • Assessing Saiph, a task-based DSL for high-performance computational fluid dynamics 

    Macià Sorrosal, Sandra; Martínez Ferrer, Pedro José; Ayguadé Parra, Eduard; Beltran Querol, Vicenç (Elsevier, 2023-10)
    Article
    Accés restringit per política de l'editorial
    Scientific applications face the challenge of efficiently exploiting increasingly complex parallel and distributed systems. Developing hand-tuned codes is a time-consuming, tedious and hardly reusable task. Reaching high ...
  • RISC-V for genome data analysis: opportunities and challenges 

    López Villellas, Lorien; Pineda Sánchez, Esteve; Badouh, Asaf; Marco-Sola, Santiago; Ibáñez Marín, Pablo; Alastruey Benedé, Jesús; Moretó Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based ...
  • Property rights in servitisation: a practical assessment with reused computers 

    Roura Salietti, Mireya; Navarro Moldes, Leandro; Meseguer Pallarès, Roc (Springer, 2022)
    Text en actes de congrés
    Accés obert
    The circular economy of computers is about producing fewer, more durable and reusable products while investing in expanding their life span through a functional service economy. Reuse is often mentioned as a sustainable ...
  • Boosting point cloud search with a vector unit 

    Exenberger Becker, Pedro Henrique; Arnau Montañés, José María; González Colás, Antonio María (2023)
    Report de recerca
    Accés obert
    Modern robots collect and process point clouds to perform accurate registration and segmentation. The most time-consuming kernel within point cloud processing -namely neighbor search- relies on appropriate data structures, ...
  • Analyzing and improving hardware modeling of Accel-Sim 

    Huerta Gañán, Rodrigo; Abaie Shoushtary, Mojtaba; González Colás, Antonio María (2023-10)
    Report de recerca
    Accés obert
    GPU architectures have become popular for executing generalpurpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern ...
  • Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective 

    Alonso García, Martí; Andreu Gerique, David; Canal Corretger, Ramon; Di Carlo, Stefano; Chenet, Cristiano; Costa Prats, Juan José; Gironès, Andreu; Gizopoulos, Dimitris; Karakostas, Vasileios; Otero Calviño, Beatriz; Papadimitriou, George; Rodríguez Luna, Eva; Savino, Alessandro (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services. This software stack ...
  • NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS 

    Pavanello, Fabio; Marchand, Cedric; O’Connor, Ian; Orobtchouk, Regis; Mandorlo, Fabien; Letartre, Xavier; Cueff, Sebastien; Brando Guillaumes, Axel; Cazorla Almeida, Francisco Javier; Canal Corretger, Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. ...
  • Energy hardware and workload aware job scheduling towards interconnected HPC environments 

    D'Amico, Marco; Corbalán González, Julita (2021-06-17)
    Article
    Accés obert
    New HPC machines are getting close to the exascale. Power consumption for those machines has been increasing, and researchers are studying ways to reduce it. A second trend is HPC machines' growing complexity, with increasing ...
  • Charging of the ABR service in ATM networks: a numerical example 

    Cerdà Alabern, Llorenç; Casals Torres, Olga M. (Institute of Electrical and Electronics Engineers (IEEE), 1998-04)
    Article
    Accés obert
    The Available Bit Rate service (ABR) is a "best effort" service intended for traffic which imposes no bound on delay or delay variation. The network guarantees a Minimum Cell Rate (MCR) for an ABR source, which is negotiated ...
  • δLTA:: Decoupling camera sampling from processing to avoid redundant computations in the vision pipeline 

    Taranco Serna, Raúl; Arnau Montañés, José María; González Colás, Antonio María (Association for Computing Machinery (ACM), 2023)
    Text en actes de congrés
    Accés obert
    Continuous Vision (CV) systems are essential for emerging applications like Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR). A standard CV System-on-a-Chip (SoC) pipeline includes a frontend for image capture ...
  • SLIDEX: Sliding window extension for image processing 

    Taranco Serna, Raúl; Arnau Montañés, José María; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Text en actes de congrés
    Accés obert
    With the rising need for efficient image processing in emerging applications such as Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR), many existing solutions do not meet their performance and energy efficiency ...
  • QeiHaN: An energy-efficient DNN accelerator that leverages log quantization in NDP architectures 

    Khabbazan, Bahareh; Riera Villanueva, Marc; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2023)
    Comunicació de congrés
    Accés obert
    The constant growth of DNNs makes them challenging to implement and run efficiently on traditional computecentric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip ...

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