Departament d'Arquitectura de Computadors

Enviaments recents

  • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

    Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
    Text en actes de congrés
    Accés obert
    High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...

  • Towards blockchain-enabled wireless mesh networks 

    Selimi, Mennan; Kabbinale, A.R.; Ali, A.; Navarro Moldes, Leandro; Sathiaseelan, Arjuna (Association for Computing Machinery (ACM), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Recently, mesh networking and blockchain are two of the hottest technologies in the telecommunications industry. Combining both can reformulate Internet access. While mesh networking makes connecting to the Internet easy ...

  • Perfil de las ingenieras TIC versus el de otras mujeres STEM 

    Olmedo Torre, Noelia; Sánchez Carracedo, Fermín; Salán Ballesteros, Maria Núria; López Álvarez, David; Pérez Poch, Antoni; López Beltrán, Mireia (Asociación de Enseñantes Universitarios de la Informática (AENUI), 2018)
    Text en actes de congrés
    Accés obert
    The low percentage of enrollment of females in the STEM university degrees has been and is the subject of research. Moreover, the low female presence is not evenly distributed in all STEM studies. In certain areas, such ...

  • Visibility rendering order: Improving energy efficiency on mobile GPUs through frame coherence 

    Lucas Casamayor, Enrique de; Marcuello Pascual, Pedro; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2018-08-20)
    Article
    Accés obert
    During real-time graphics rendering, objects are processed by the GPU in the order they are submitted by the CPU, and occluded surfaces are often processed even though they will end up not being part of the final image, ...

  • Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
    Article
    Accés obert
    Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...

  • RPR: a random replacement policy with limited pathological replacements 

    Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...

  • Design and integration of hierarchical-placement multi-level caches for real-Time systems 

    Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Enabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...

  • A novel register renaming technique for out-of-order processors 

    Tabani, Hamid; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Raventos, Aquiles (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Modern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for ...

  • On the benefits of elastic spectrum management in multi-hour filterless metro networks 

    Pedreno Manresa, J.J.; Izquierdo Zaragoza, José Luis; Cugini, Filippo; Pavón Mariño, Pablo (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The dawn of 5G is pushing operators to deploy high-capacity, agile networks capable of adapting to time-varying traffic patterns, especially into metro sections. ROADMs are key enablers for agility in the optical layer, ...

  • SBAR: SDN flow-based monitoring and application recognition 

    Suárez-Varela Maciá, José Rafael; Barlet Ros, Pere (Association for Computing Machinery (ACM), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    We present SBAR, a monitoring system compliant with OpenFlow that provides flow-level measurement reports similar to those of NetFlow in traditional networks, but additionally enriched with labels that classify flows at ...

  • Gelly-scheduling: distributed graph processing for service placement in community networks 

    Coimbra, Miguel E.; Selimi, Mennan; Francisco, Alexandre P.; Freitag, Fèlix; Veiga, Luis (Association for Computing Machinery (ACM), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Community networks (CNs) have seen an increase in the last fifteen years. Their members contact nodes which operate Internet proxies, web servers, user file storage and video streaming services, to name a few. Detecting ...

  • High performance robotic computing as an enabler for cooperative flights 

    Camargo Forero, Leonardo; Royo Chic, Pablo; Prats Menéndez, Xavier (2018)
    Comunicació de congrés
    Accés restringit per política de l'editorial
    High Performance Robotic Computing (HPRC) is a new computer science field, which aims at exploiting traditional High Performance Computing (HPC) features, strategies and technologies in the context of multi-robot settings ...

Mostra'n més