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Runtime-assisted cache coherence deactivation in task parallel programs
dc.contributor.author | Caheny, Paul |
dc.contributor.author | Álvarez Martí, Lluc |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Moretó Planas, Miquel |
dc.contributor.author | Casas, Marc |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2018-12-05T08:35:37Z |
dc.date.available | 2018-12-05T08:35:37Z |
dc.date.issued | 2018 |
dc.identifier.citation | Caheny, P., Álvarez, L., Valero, M., Moreto, M., Casas, M. Runtime-assisted cache coherence deactivation in task parallel programs. A: International Conference for High Performance Computing, Networking, Storage, and Analysis. "Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis: Dallas, TX, USA, November 11-16, 2018". New York: Association for Computing Machinery (ACM), 2018, p. 1-12. |
dc.identifier.uri | http://hdl.handle.net/2117/125393 |
dc.description.abstract | With increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data as private or shared, and disable coherence for private data. However, existing classification methods suffer from inaccuracies and require complex hardware support with limited scalability. This paper proposes a hardware/software co-designed approach: the runtime system identifies data that is guaranteed by the programming model semantics to not require coherence and notifies the microarchitecture. The microarchitecture deactivates coherence for this private data and powers off unused directory capacity. Our proposal reduces directory accesses to just 26% of the baseline system, and supports a 64x smaller directory with only 2.8% performance degradation. By dynamically calibrating the directory size our proposal saves 86% of dynamic energy consumption in the directory without harming performance. |
dc.description.sponsorship | This work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272) and by the European Unions Horizon 2020 research and innovation programme (grant agreements 671697 and 779877). M. Moreto has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | Association for Computing Machinery (ACM) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles |
dc.subject.lcsh | Memory management (Computer science) |
dc.subject.lcsh | Parallel programming (Computer science) |
dc.subject.lcsh | Cache memory |
dc.subject.other | Memory architecture |
dc.subject.other | Runtime environment |
dc.title | Runtime-assisted cache coherence deactivation in task parallel programs |
dc.type | Conference report |
dc.subject.lemac | Gestió de memòria (Informàtica) |
dc.subject.lemac | Programació en paral·lel (Informàtica) |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://dl.acm.org/citation.cfm?id=3291703 |
dc.rights.access | Open Access |
local.identifier.drac | 23529198 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1272 |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/V PRI/2014 SGR 1051 |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ |
dc.relation.projectid | info:eu-repo/grantAgreement/AEI/RYC-2016-21104 |
dc.relation.projectid | info:eu-repo/grantAgreement/HiPEAC (NoE - Unión Europea)/IST-2003-004408 |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology/Mont-Blanc 3 |
dc.relation.projectid | info:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020 |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO/PE2013-2016/RYC-2016-21104 |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ |
local.citation.author | Caheny, P.; Álvarez, L.; Valero, M.; Moreto, M.; Casas, M. |
local.citation.contributor | International Conference for High Performance Computing, Networking, Storage, and Analysis |
local.citation.pubplace | New York |
local.citation.publicationName | Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis: Dallas, TX, USA, November 11-16, 2018 |
local.citation.startingPage | 1 |
local.citation.endingPage | 12 |