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A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Petit Silvestre, Jordi |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2018-11-15T07:14:50Z |
dc.date.available | 2018-11-15T07:14:50Z |
dc.date.issued | 2018 |
dc.identifier.citation | Cortadella, J., Petit, J. A hierarchical mathematical model for automatic pipelining and allocation using elastic systems. A: Asilomar Conference on Signals, Systems, and Computers. "Conference record of the Fifty-First Asilomar Conference on Signals, Systems & Computers: October 29-November 1, 2017 Pacific Grove, California". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 115-120. |
dc.identifier.isbn | 978-1-5386-1823-3 |
dc.identifier.uri | http://hdl.handle.net/2117/124265 |
dc.description.abstract | The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical task for the delivery of high-quality solutions. Time elasticity opens a new avenue of optimizations that can be applied after HLS and before logic synthesis, proposing new sequential transformations that expand beyond classical retiming and enlarge the register-transfer level (RTL) exploration space. This paper proposes a mathematical model for RTL transformations that exploit elasticity to select the best implementation for each functional unit and add pipeline registers to increase performance. Two simple examples are used to validate the effectiveness and potential benefits of the model. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Informàtica teòrica |
dc.subject.lcsh | Logic circuits |
dc.subject.lcsh | Field programmable gate arrays |
dc.subject.lcsh | Logic design |
dc.subject.other | Elasticity |
dc.subject.other | High level synthesis |
dc.subject.other | Logic synthesis |
dc.subject.other | Mathematical transformations |
dc.subject.other | Behavioral level |
dc.subject.other | Design optimization |
dc.subject.other | Design space exploration |
dc.subject.other | Functional units |
dc.subject.other | High-quality solutions |
dc.subject.other | Pipeline registers |
dc.subject.other | Potential benefits |
dc.subject.other | Register transfer level |
dc.subject.other | Hierarchical systems |
dc.title | A hierarchical mathematical model for automatic pipelining and allocation using elastic systems |
dc.type | Conference report |
dc.subject.lemac | Circuits lògics |
dc.subject.lemac | Matrius de portes programables per l'usuari |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ACSSC.2017.8335149 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8335149 |
dc.rights.access | Open Access |
local.identifier.drac | 23423043 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2013-46181-C2-1-R/ES/MODELOS Y METODOS COMPUTACIONALES PARA DATOS MASIVOS ESTRUCTURADOS/ |
dc.relation.projectid | info:eu-repo/grantAgreement/AGAUR/2014 SGR 1034 |
local.citation.author | Cortadella, J.; Petit, J. |
local.citation.contributor | Asilomar Conference on Signals, Systems, and Computers |
local.citation.publicationName | Conference record of the Fifty-First Asilomar Conference on Signals, Systems & Computers: October 29-November 1, 2017 Pacific Grove, California |
local.citation.startingPage | 115 |
local.citation.endingPage | 120 |