A hierarchical mathematical model for automatic pipelining and allocation using elastic systems
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical task for the delivery of high-quality solutions. Time elasticity opens a new avenue of optimizations that can be applied after HLS and before logic synthesis, proposing new sequential transformations that expand beyond classical retiming and enlarge the register-transfer level (RTL) exploration space. This paper proposes a mathematical model for RTL transformations that exploit elasticity to select the best implementation for each functional unit and add pipeline registers to increase performance. Two simple examples are used to validate the effectiveness and potential benefits of the model.
CitationCortadella, J., Petit, J. A hierarchical mathematical model for automatic pipelining and allocation using elastic systems. A: Asilomar Conference on Signals, Systems, and Computers. "Conference record of the Fifty-First Asilomar Conference on Signals, Systems & Computers: October 29-November 1, 2017 Pacific Grove, California". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 115-120.
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