The design and performance of a conflict-avoiding cache
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint.
CitationTopham, N., González, A., González, J. The design and performance of a conflict-avoiding cache. A: Annual IEEE/ACM International Symposium on Microarchitecture. "MICRO 30: proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 71-80.
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