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The design and performance of a conflict-avoiding cache
dc.contributor.author | Topham, Nigel |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | González González, José |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-21T10:06:09Z |
dc.date.available | 2017-02-21T10:06:09Z |
dc.date.issued | 1997 |
dc.identifier.citation | Topham, N., González, A., González, J. The design and performance of a conflict-avoiding cache. A: Annual IEEE/ACM International Symposium on Microarchitecture. "MICRO 30: proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture". San Francisco: Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 71-80. |
dc.identifier.isbn | 0-8186-7977-8 |
dc.identifier.uri | http://hdl.handle.net/2117/101279 |
dc.description.abstract | High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Cache memory |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Cache storage |
dc.subject.other | Memory architecture |
dc.subject.other | Performance evaluation |
dc.subject.other | Parallel machines |
dc.subject.other | Parallel architectures |
dc.subject.other | Performance evaluation |
dc.subject.other | Instruction sets |
dc.title | The design and performance of a conflict-avoiding cache |
dc.type | Conference report |
dc.subject.lemac | Memòria cau |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/MICRO.1997.645799 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/645799/ |
dc.rights.access | Open Access |
local.identifier.drac | 2338473 |
dc.description.version | Postprint (published version) |
local.citation.author | Topham, N.; González, A.; González, J. |
local.citation.contributor | Annual IEEE/ACM International Symposium on Microarchitecture |
local.citation.pubplace | San Francisco |
local.citation.publicationName | MICRO 30: proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture |
local.citation.startingPage | 71 |
local.citation.endingPage | 80 |