Browsing by Author "González Colás, Antonio María"
Now showing items 1-20 of 228
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2018 International Symposium on Computer Architecture influential paper award
(2018-07-01)
Article
Open AccessThe International Symposium on Computer Architecture (ISCA) recognizes every year the most influential paper published in this conference 15 years earlier, based on its impact on research, development, products or ideas. ... -
A case for acoustic wave detectors for soft-errors
(2016-01-01)
Article
Restricted access - publisher's policyThe continuing decrease in dimensions and operating voltage of transistors has increased their sensitivity against radiation phenomena, making soft errors an important challenge in future microprocessors. New techniques ... -
A co-designed HW/SW approach to general purpose program acceleration using a programmable functional unit
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyIn this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor in a complexity-effective way. Code is transformed and ... -
A cost-effective clustered architecture
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessIn current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute ... -
A detailed methodology to compute soft error rates in advanced technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Restricted access - publisher's policySystem reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ... -
A Dynamically Adaptable Hardware Transactional Memory
(IEEE Computer Society Publications, 2010)
Conference report
Open AccessMost Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-place in memory and resolve conflicts ... -
A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe paper proposes an algorithm for computing symmetric eigenvalues and eigenvectors that uses a one-sided Jacobi approach and is targeted to a multicomputer in which nodes can be arranged as a two-dimensional mesh with ... -
A low-power hardware accelerator for ORB feature extraction in self-driving cars
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessSimultaneous Localization And Mapping (SLAM) is a key component for autonomous navigation. SLAM consists of building and creating a map of an unknown environment while keeping track of the exploring agent's location within ... -
A low-power, high-performance speech recognition accelerator
(Institute of Electrical and Electronics Engineers (IEEE), 2019-12-01)
Article
Open AccessAutomatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at high energy cost, not being affordable for the tiny power-budgeted mobile devices. ... -
A methodology for user-oriented scalability analysis
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessScalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ... -
A methodology for user-oriented scalability analysis.
(IEEE, 1997-07-14)
Conference report
Open AccessScalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ... -
A novel register renaming technique for out-of-order processors
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Restricted access - publisher's policyModern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for ... -
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
(IEEE Computer Society Publications, 2012)
Conference report
Restricted access - publisher's policyIn view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ... -
A partial breadth-first execution model for prolog
(Institute of Electrical and Electronics Engineers (IEEE), 1994)
Conference report
Open AccessMEM (Multipath Execution Model) is a novel model for the execution of Prolog programs which combines a depth-first and breadth-first exploration of the search tree. The breadth-first search allows more than one path of the ... -
A programmable accelerator for streaming automatic speech recognition on edge devices
(2022)
Conference report
Open AccessAutomatic Speech Recognition (ASR) is quickly becoming a mainstream technology, mainly driven by the outstanding accuracy achieved by modern systems based on machine learning. However, these systems often require billions ... -
A quantitative assessment of thread-level speculation techniques
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Conference report
Open AccessSpeculative thread-level parallelism has been recently proposed as an alternative source of parallelism that can boost the performance for applications where independent threads are hard to find. Several schemes to exploit ... -
A selective logging mechanism for hardware transactional memory systems
(2011-09-19)
Research report
Open AccessLog-based Hardware Transactional Memory (HTM) systems offer an elegant solution to handle speculative data that overflow transactional L1 caches. By keeping the pre-transactional values on a software-resident log, speculative ... -
A software-hardware hybrid steering mechanism for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessClustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ... -
A study of the communication cost of the FFT on torus multicomputers
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessThe computation of a one-dimensional FFT on a c-dimensional torus multicomputer is analyzed. Different approaches are proposed which differ in the way they use the interconnection network. The first approach is based on ... -
A survey of near-data processing architectures for neural networks
(2022-01-17)
Article
Open AccessData-intensive workloads and applications, such as machine learning (ML), are fundamentally limited by traditional computing systems based on the von-Neumann architecture. As data movement operations and energy consumption ...
