Browsing by Author "González González, José"
Now showing items 1-16 of 16
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A software-hardware hybrid steering mechanism for clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessClustered microarchitectures provide a promising paradigm to solve or alleviate the problems of increasing microprocessor complexity and wire delays. High- performance out-of-order processors rely on hardware-only steering ... -
Control speculation for energy-efficient next-generation superscalar processors
(2006-03)
Article
Open AccessConventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, ... -
Control-flow speculation through value prediction for superscalar processors
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessIn this paper, we introduce a new branch predictor that predicts the outcomes of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The ... -
Delaying physical register allocation trought virtual-physical registers
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessRegister file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ... -
Distributing the frontend for temperature reduction
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessDue to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the heat generated, and the performance impact ... -
Dynamic cluster resizing
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Conference report
Open AccessProcessor resources required for an effective execution of an application vary across different sections. We propose to take advantage of clustering to turn-off resources that do not contribute to improve performance. ... -
Efficient resources assignment schemes for clustered multithreaded processors
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Conference report
Open AccessNew feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate ... -
Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessIn this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism ... -
Late allocation and early release of physical registers
(2004-10)
Article
Open AccessThe register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ... -
Power-aware control speculation through selective throttling
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Conference report
Open AccessWith the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors ... -
The design and performance of a conflict-avoiding cache
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessHigh performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. ... -
Thermal-aware clustered microarchitectures
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
Conference report
Open AccessAs frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it generates are increasing at the same rate. ... -
Understanding the thermal implications of multicore architectures
(2007-08)
Article
Open AccessMulticore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations ... -
Using MCD-DVS for dynamic thermal management performance improvement
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
Conference report
Open AccessWith chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for ... -
Virtual registers
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThe number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ... -
Virtual-physical registers
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessA novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pipeline, instead of doing it in the decode ...
