La principal finalitat del grup és investigar en el camp del disseny arquitectònic dels futurs processadores tenint en compte especialment els nous aspectes tecnològics que el condicionaran, tant per processadors d'alt rendiment com pels destinats a l'electrònica de consum.

El grup continua estant format per la mateixa base de professors doctors que ja vam obtenir l'ajut en les convocatòries SGR tant l'any 2005 com el 2009. Està format per professors del Dpt. d'Arquitectura de Computadors de la UPC juntament amb dos professors de la URV. A aquesta base s'hi ha afegit respecte la darrera convocatòria 4 nous membres doctors amb contracte post-doctoral. La variabilitat cal buscar-la en els membre pre-doctors, on es donen de baixa aquells que ja han acabat la tesi i es donen d'alta els nous estudiants de doctorat.

Volem destacar que el grup ha produït al voltant de 500 articles en congressos i revistes d'alt impacte, més de 100 patents i ha dirigit mes de 25 tesis.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

Enviaments recents

  • MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment 

    Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Text en actes de congrés
    Accés obert
    Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ...
  • HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation 

    Kumar, Rakesh; Cano, José; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. ...
  • Removing checks in dynamically typed languages through efficient profiling 

    Dot, Gem; Martinez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Dynamically typed languages increase programmer's productivity at the expense of some runtime overheads to manage the types of variables, since they are not declared at compile time and can change at runtime. One of the ...
  • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Comunicació de congrés
    Accés restringit per política de l'editorial
    This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...
  • Low-power automatic speech recognition through a mobile GPU and a Viterbi accelerator 

    Yazdani Aminabadi, Reza; Segura Salvador, Albert; Arnau Montañés, José María; González Colás, Antonio María (2017-04-12)
    Article
    Accés obert
    Automatic speech recognition (ASR) has become a core technology for mobile devices. Delivering real-time and accurate ASR has a huge computational cost, which is challenging to achieve in tightly energy-constrained platforms ...
  • UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition 

    Yazdani Aminabadi, Reza; Arnau Montañés, José María; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Accurate, real-time Automatic Speech Recognition (ASR) requires huge memory storage and computational power. The main bottleneck in state-of-the-art ASR systems is the Viterbi search on a Weighted Finite State Transducer ...
  • An ultra low-power hardware accelerator for acoustic scoring in speech recognition 

    Tabani, Hamid; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Accurate, real-time Automatic Speech Recognition (ASR) comes at a high energy cost, so accuracy has often to be sacrificed in order to fit the strict power constraints of mobile systems. However, accuracy is extremely ...
  • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

    Cortadella Fortuny, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
    Report de recerca
    Accés obert
    The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...
  • Branch classification to control instruction fetch in simultaneous multithreaded architectures 

    Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    In simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ...
  • Via-configurable transistors array: a regular design technique to improve ICs yield 

    Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Text en actes de congrés
    Accés obert
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...
  • Virtual registers 

    González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ...
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

    Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
    Text en actes de congrés
    Accés obert
    In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...

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