ARCO - Microarquitectura i Compiladors
Les activitats de recerca del grup ARCO es centren en l'area de arquitectura de computadors, compiladors i el processament en paral·lel, amb especial èmfasi en la microarquitectura i les tècniques de generació de codi per a sistemes de computació fiables i eficients energèticament. Un dels seus principals enfocaments actuals és sobre sistemes de computació intel·ligents, on l'objectiu és dissenyar noves arquitectures per a l'aprenentatge automàtic, la visió per computador i el processament del llenguatge. L'altre enfocament principal és en els processadors gràfics tant per a càrregues de treball de propòsit general com per a aplicacions gràfiques.
El grup està format per professors i estudiants de la Universitat Politècnica de Catalunya, la Universitat de Múrcia i la Universitat Rovira i Virgili. El grup té un llarg historial de publicacions científiques, amb més de 500 articles d'investigació, i transferències de tecnologia, amb més de 50 patents.
Las actividades de investigación del grupo ARCO se centran en el área de arquitectura de computadores, compiladores y el procesamiento en paralelo, con especial énfasis en la microarquitectura y las técnicas de generación de código para sistemas de computación fiables y eficientes energéticamente. Uno de sus principales enfoques actuales es sobre sistemas de computación inteligentes, donde el objetivo es diseñar nuevas arquitecturas para el aprendizaje automático, la visión por computador y el procesamiento del lenguaje. El otro enfoque principal es en los procesadores gráficos tanto para cargas de trabajo de propósito general como para aplicaciones gráficas.
El grupo está formado por profesores y estudiantes de la Universidad Politécnica de Catalunya, la Universidad de Murcia y la Universidad Rovira i Virgili. El grupo tiene un largo historial de publicaciones científicas, con más de 500 artículos de investigación, y transferencias de tecnología, con más de 50 patentes.
The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.
The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.
The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.
The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.
Collections in this community
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Articles de revista [64]
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Reports de recerca [11]
Recent Submissions
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Sliding window support for image processing in autonomous vehicles
(2022)
Conference report
Open AccessCamera-based autonomous driving extensively ma-nipulates images for object detection, object tracking, or camera-based localization tasks. Therefore, efficient and fast image processing is crucial in those systems. ... -
DTexL: Decoupled raster pipeline for texture locality
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessContemporary GPU architectures have multiple shader cores and a scheduler that distributes work (threads) among them, focusing on load balancing. These load balancing techniques favor thread distributions that are detrimental ... -
Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads
(2022-07-18)
Article
Open AccessGPGPU architectures have become the dominant platform for massively parallel workloads, delivering high performance and energy efficiency for popular applications such as machine learning, computer vision or self-driving ... -
E-BATCH: Energy-efficient and high-throughput RNN batching
(2022-03)
Article
Open AccessRecurrent Neural Network (RNN) inference exhibits low hardware utilization due to the strict data dependencies across time-steps. Batching multiple requests can increase throughput. However, RNN batching requires a large ... -
CREW: Computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs
(2022-08-01)
Article
Open AccessDeep Neural Networks (DNNs) have achieved tremendous success for cognitive applications. The core operation in a DNN is the dot product between quantized inputs and weights. Prior works exploit the weight/input repetition ... -
Vector extensions in COTS processors to increase guaranteed performance in real-time systems
(2022-08-31)
Article
Open AccessThe need for increased application performance in high-integrity systems like those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future ... -
A programmable accelerator for streaming automatic speech recognition on edge devices
(2022)
Conference report
Open AccessAutomatic Speech Recognition (ASR) is quickly becoming a mainstream technology, mainly driven by the outstanding accuracy achieved by modern systems based on machine learning. However, these systems often require billions ... -
XFeatur: Hardware feature extraction for DNN auto-tuning
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessIn this work, we extend the auto-tuning process of the state-of-the-art TVM framework with XFeatur; a tool that extracts new meaningful hardware-related features that improve the quality of the representation of the search ... -
MEGsim: A Novel methodology for efficient simulation of graphics workloads in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessAn important drawback of cycle-accurate microarchitectural simulators is that they are several orders of magnitude slower than the system they model. This becomes an important issue when simulations have to be repeated ... -
Dynamic sampling rate: harnessing frame coherence in graphics applications for energy-efficient GPUs
(Springer Nature, 2022)
Article
Open AccessIn real-time rendering, a 3D scene is modelled with meshes of triangles that the GPU projects to the screen. They are discretized by sampling each triangle at regular space intervals to generate fragments which are then ... -
DTM-NUCA: dynamic texture mapping-NUCA for energy-efficient graphics rendering
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessModern mobile GPUs integrate an increasing number of shader cores to speedup the execution of graphics workloads. Each core integrates a private Texture Cache to apply texturing effects on objects, which is backed-up by a ... -
TCOR: a tile cache with optimal replacement
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessCache Replacement Policies are known to have an important impact on hit rates. The OPT replacement policy [27] has been formally proven as optimal for minimizing misses. Due to its need to look far ahead for future memory ...
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