Les activitats de recerca del grup ARCO es centren en l'area de arquitectura de computadors, compiladors i el processament en paral·lel, amb especial èmfasi en la microarquitectura i les tècniques de generació de codi per a sistemes de computació fiables i eficients energèticament. Un dels seus principals enfocaments actuals és sobre sistemes de computació intel·ligents, on l'objectiu és dissenyar noves arquitectures per a l'aprenentatge automàtic, la visió per computador i el processament del llenguatge. L'altre enfocament principal és en els processadors gràfics tant per a càrregues de treball de propòsit general com per a aplicacions gràfiques.

El grup està format per professors i estudiants de la Universitat Politècnica de Catalunya, la Universitat de Múrcia i la Universitat Rovira i Virgili. El grup té un llarg historial de publicacions científiques, amb més de 500 articles d'investigació, i transferències de tecnologia, amb més de 50 patents.

http://futur.upc.edu/ARCO

Las actividades de investigación del grupo ARCO se centran en el área de arquitectura de computadores, compiladores y el procesamiento en paralelo, con especial énfasis en la microarquitectura y las técnicas de generación de código para sistemas de computación fiables y eficientes energéticamente. Uno de sus principales enfoques actuales es sobre sistemas de computación inteligentes, donde el objetivo es diseñar nuevas arquitecturas para el aprendizaje automático, la visión por computador y el procesamiento del lenguaje. El otro enfoque principal es en los procesadores gráficos tanto para cargas de trabajo de propósito general como para aplicaciones gráficas.

El grupo está formado por profesores y estudiantes de la Universidad Politécnica de Catalunya, la Universidad de Murcia y la Universidad Rovira i Virgili. El grupo tiene un largo historial de publicaciones científicas, con más de 500 artículos de investigación, y transferencias de tecnología, con más de 50 patentes.

http://futur.upc.edu/ARCO

The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.

The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.

http://futur.upc.edu/ARCO

The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.

The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.

http://futur.upc.edu/ARCO

Enviaments recents

  • SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems 

    Vallero, Alessandro; Savino, Alessandro; Chatzidimitriou, Athanansios; Kaliorakis, Manolis; Kooli, Maha; Riera Villanueva, Marc; Di Natale, Giorgio; Bosio, Alberto; Canal Corretger, Ramon; Gizopoulos, Dimitris; Di Carlo, Stefano (Institute of Electrical and Electronics Engineers (IEEE), 2018-01-01)
    Article
    Accés obert
    Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different ...
  • Computation reuse in DNNs by exploiting input similarity 

    Riera Villanueva, Marc; Arnau Montañés, José María; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
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    In recent years, Deep Neural Networks (DNNs) have achieved tremendous success for diverse problems such as classification and decision making. Efficient support for DNNs on CPUs, GPUs and accelerators has become a prolific ...
  • The dark side of DNN pruning 

    Yazdani Aminabadi, Reza; Arnau Montañés, José María; González Raventos, Aquiles; Riera Villanueva, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
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    DNN pruning has been recently proposed as an effective technique to improve the energy-efficiency of DNN-based solutions. It is claimed that by removing unimportant or redundant connections, the pruned DNN delivers higher ...
  • Visibility rendering order: Improving energy efficiency on mobile GPUs through frame coherence 

    Lucas Casamayor, Enrique de; Marcuello Pascual, Pedro; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2018-08-20)
    Article
    Accés obert
    During real-time graphics rendering, objects are processed by the GPU in the order they are submitted by the CPU, and occluded surfaces are often processed even though they will end up not being part of the final image, ...
  • A novel register renaming technique for out-of-order processors 

    Tabani, Hamid; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Raventos, Aquiles (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Modern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for ...
  • Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm 

    Amat Bertran, Esteve; García Almudéver, Carmen; Aymerich, N.; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014-10-01)
    Article
    Accés obert
    3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ...
  • MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment 

    Kaliorakis, Manolis; Gizopoulos, Dimitris; Canal Corretger, Ramon; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Text en actes de congrés
    Accés obert
    Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ...
  • HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation 

    Kumar, Rakesh; Cano, José; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. ...
  • Removing checks in dynamically typed languages through efficient profiling 

    Dot, Gem; Martinez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    Dynamically typed languages increase programmer's productivity at the expense of some runtime overheads to manage the types of variables, since they are not declared at compile time and can change at runtime. One of the ...
  • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Comunicació de congrés
    Accés restringit per política de l'editorial
    This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...
  • Low-power automatic speech recognition through a mobile GPU and a Viterbi accelerator 

    Yazdani Aminabadi, Reza; Segura Salvador, Albert; Arnau Montañés, José María; González Colás, Antonio María (2017-04-12)
    Article
    Accés obert
    Automatic speech recognition (ASR) has become a core technology for mobile devices. Delivering real-time and accurate ASR has a huge computational cost, which is challenging to achieve in tightly energy-constrained platforms ...
  • UNFOLD: a memory-efficient speech recognizer using on-the-fly WFST composition 

    Yazdani Aminabadi, Reza; Arnau Montañés, José María; González Colás, Antonio María (Association for Computing Machinery (ACM), 2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Accurate, real-time Automatic Speech Recognition (ASR) requires huge memory storage and computational power. The main bottleneck in state-of-the-art ASR systems is the Viterbi search on a Weighted Finite State Transducer ...

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