ARCO - Microarquitectura i Compiladors
Les activitats de recerca del grup ARCO es centren en l'area de arquitectura de computadors, compiladors i el processament en paral·lel, amb especial èmfasi en la microarquitectura i les tècniques de generació de codi per a sistemes de computació fiables i eficients energèticament. Un dels seus principals enfocaments actuals és sobre sistemes de computació intel·ligents, on l'objectiu és dissenyar noves arquitectures per a l'aprenentatge automàtic, la visió per computador i el processament del llenguatge. L'altre enfocament principal és en els processadors gràfics tant per a càrregues de treball de propòsit general com per a aplicacions gràfiques.
El grup està format per professors i estudiants de la Universitat Politècnica de Catalunya, la Universitat de Múrcia i la Universitat Rovira i Virgili. El grup té un llarg historial de publicacions científiques, amb més de 500 articles d'investigació, i transferències de tecnologia, amb més de 50 patents.
Las actividades de investigación del grupo ARCO se centran en el área de arquitectura de computadores, compiladores y el procesamiento en paralelo, con especial énfasis en la microarquitectura y las técnicas de generación de código para sistemas de computación fiables y eficientes energéticamente. Uno de sus principales enfoques actuales es sobre sistemas de computación inteligentes, donde el objetivo es diseñar nuevas arquitecturas para el aprendizaje automático, la visión por computador y el procesamiento del lenguaje. El otro enfoque principal es en los procesadores gráficos tanto para cargas de trabajo de propósito general como para aplicaciones gráficas.
El grupo está formado por profesores y estudiantes de la Universidad Politécnica de Catalunya, la Universidad de Murcia y la Universidad Rovira i Virgili. El grupo tiene un largo historial de publicaciones científicas, con más de 500 artículos de investigación, y transferencias de tecnología, con más de 50 patentes.
The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.
The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.
The research activities of the ARCO group focus on computer architecture, compilers and parallel processing, with special emphasis on microarchitecture and code generation techniques for energy-efficient and reliable computing systems. One of its main current focuses is on intelligent computing systems, where the goal is to devise novel architectures for machine learning, computer vision, language processing. The other major focus is on graphics processors both for general-purpose and graphics workloads.
The group consists of faculty members and students from Polytechnic University of Catalonia, University of Murcia and Rovira i Virgili University. The group has a long track record of scientific publications, with more than 500 research papers, and technology transfers, with more than 50 patents.
Collections in this community
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Articles de revista [68]
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Reports de recerca [13]
Recent Submissions
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SLIDEX: A novel architecture for sliding window processing
(Association for Computing Machinery (ACM), 2024)
Conference report
Open AccessEfficient image processing is increasingly crucial in constrained embedded and real-time platforms, especially in emerging applications such as Autonomous Driving (AD) or Augmented/Virtual Reality (AR/VR). A commonality ... -
DNA-TEQ: an adaptive exponential quantization of tensors for DNN inference
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessQuantization is commonly used in Deep Neural Networks (DNNs) to reduce the storage and computational complexity by decreasing the arithmetical precision of activations and weights, a.k.a. tensors. Efficient hardware ... -
Boosting point cloud search with a vector unit
(2023)
Research report
Open AccessModern robots collect and process point clouds to perform accurate registration and segmentation. The most time-consuming kernel within point cloud processing -namely neighbor search- relies on appropriate data structures, ... -
Analyzing and improving hardware modeling of Accel-Sim
(2023-10)
Research report
Open AccessGPU architectures have become popular for executing generalpurpose programs. Their many-core architecture supports a large number of threads that run concurrently to hide the latency among dependent instructions. In modern ... -
δLTA:: Decoupling camera sampling from processing to avoid redundant computations in the vision pipeline
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessContinuous Vision (CV) systems are essential for emerging applications like Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR). A standard CV System-on-a-Chip (SoC) pipeline includes a frontend for image capture ... -
SLIDEX: Sliding window extension for image processing
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessWith the rising need for efficient image processing in emerging applications such as Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR), many existing solutions do not meet their performance and energy efficiency ... -
QeiHaN: An energy-efficient DNN accelerator that leverages log quantization in NDP architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference lecture
Open AccessThe constant growth of DNNs makes them challenging to implement and run efficiently on traditional computecentric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip ... -
Boustrophedonic frames: Quasi-optimal L2 caching for textures in GPUs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessLiterature is plentiful in works exploiting cache locality for GPUs. A majority of them explore replacement or bypassing policies. In this paper, however, we surpass this exploration by fabricating a formal proof for a ... -
Exploiting kernel compression on BNNs
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessBinary Neural Networks (BNNs) are showing tremen-dous success on realistic image classification tasks. Notably, their accuracy is similar to the state-of-the-art accuracy obtained by full-precision models tailored to edge ... -
K-D Bonsai: ISA-extensions to compress K-D trees for autonomous driving tasks
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessAutonomous Driving (AD) systems extensively manipulate 3D point clouds for object detection and vehicle localization. Thereby, efficient processing of 3D point clouds is crucial in these systems. In this work we propose ... -
Lightweight register file caching in collector units for GPUs
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessModern GPUs benefit from a sizable Register File (RF) to provide fine-grained thread switching. As the RF is huge and accessed frequently, it consumes a considerable share of the dynamic energy of the GPU. Designing a ... -
Simple out of order core for GPGPUs
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessGPU architectures have become popular for executing general-purpose programs which rely on having a large number of threads that run concurrently to hide the latency among dependent instructions. This approach has an ...
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