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Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
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Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ...
Automatic generation of synchronous test patterns for asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
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This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
Combining structural and symbolic methods for the verification of concurrent systems
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
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The contributions during the last few years on the structural theory of Petri nets can now be applied to formal verification. The structural theory provides methods to find efficient encoding schemes for symbolic representations ...
Complete state encoding based on the theory of regions
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
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Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ...
ATLAS, a platform for transparently developing distributed applications
(Yi Pan, Selim G. Akl, Kegin Li. Anaheim, USA, 1998)
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We discuss the design and implementation of a software development platform that allows unsophisticated programmers to include advanced features to their applications with no or very little extra information and effort. ...
High-level synthesis techniques for reducing the activity of functional units
(Association for Computing Machinery (ACM), 1995)
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Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during ...
Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
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The energy at the I/O pins is a significant part of the overall consumption of a chip. To reduce this energy, this work extends to the data bus the working zone encoding method originally applied to encoding an external ...
Optimizing CMOS circuits for low power using transistor reordering
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
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This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. ...
Structural methods for the synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
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Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based ...
RESIS: A new methodology for register optimization in software pipelining
(Springer, 1996)
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This paper presents a new technique to reduce the register pressure in pipelined schedules. A two-step approach is proposed: minimizing the SPAN of the loop and rearranging operations within a basic block. Experimental ...