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A crosstalk latch circuit design
| dc.contributor.author | Rubio Sola, Jose Antonio |
| dc.contributor.author | Pons Nin, Joan |
| dc.contributor.author | Anglada, Raimon |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
| dc.date.accessioned | 2015-04-10T17:00:16Z |
| dc.date.created | 1990 |
| dc.date.issued | 1990 |
| dc.identifier.citation | Rubio, A.; Pons, J.; Anglada, R. A crosstalk latch circuit design. A: IEEE International Midwest Symposium on Circuits and Systems. "33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990". Calgary: Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 653-656. |
| dc.identifier.isbn | 0-7803-0081-5 |
| dc.identifier.uri | http://hdl.handle.net/2117/27259 |
| dc.description.abstract | A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen |
| dc.format.extent | 4 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
| dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
| dc.subject.lcsh | Integrated circuits |
| dc.subject.other | CMOS integrated circuits |
| dc.subject.other | VLSI |
| dc.subject.other | Crosstalk |
| dc.subject.other | Digital integrated circuits |
| dc.subject.other | Flip-flops |
| dc.title | A crosstalk latch circuit design |
| dc.type | Conference report |
| dc.subject.lemac | Circuits integrats |
| dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
| dc.contributor.group | Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies |
| dc.identifier.doi | 10.1109/MWSCAS.1990.140803 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=140803 |
| dc.rights.access | Restricted access - publisher's policy |
| local.identifier.drac | 2460305 |
| dc.description.version | Postprint (published version) |
| dc.date.lift | 10000-01-01 |
| local.citation.author | Rubio, A.; Pons, J.; Anglada, R. |
| local.citation.contributor | IEEE International Midwest Symposium on Circuits and Systems |
| local.citation.pubplace | Calgary |
| local.citation.publicationName | 33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990 |
| local.citation.startingPage | 653 |
| local.citation.endingPage | 656 |