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dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorPons Nin, Joan
dc.contributor.authorAnglada, Raimon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2015-04-10T17:00:16Z
dc.date.created1990
dc.date.issued1990
dc.identifier.citationRubio, A.; Pons, J.; Anglada, R. A crosstalk latch circuit design. A: IEEE International Midwest Symposium on Circuits and Systems. "33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990". Calgary: Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 653-656.
dc.identifier.isbn0-7803-0081-5
dc.identifier.urihttp://hdl.handle.net/2117/27259
dc.description.abstractA D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen
dc.format.extent4 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits
dc.subject.otherCMOS integrated circuits
dc.subject.otherVLSI
dc.subject.otherCrosstalk
dc.subject.otherDigital integrated circuits
dc.subject.otherFlip-flops
dc.titleA crosstalk latch circuit design
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies
dc.identifier.doi10.1109/MWSCAS.1990.140803
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=140803
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac2460305
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorRubio, A.; Pons, J.; Anglada, R.
local.citation.contributorIEEE International Midwest Symposium on Circuits and Systems
local.citation.pubplaceCalgary
local.citation.publicationName33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990
local.citation.startingPage653
local.citation.endingPage656


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