A crosstalk latch circuit design

Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon

doi:10.1109/MWSCAS.1990.140803

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Rubio Sola, Jose Antonio

Pons Nin, Joan

Anglada, Raimon

Document typeConference report

Defense date1990

PublisherInstitute of Electrical and Electronics Engineers (IEEE)

Rights accessRestricted access - publisher's policy

Abstract

A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than ±Vdd, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen

CitationRubio, A.; Pons, J.; Anglada, R. A crosstalk latch circuit design. A: IEEE International Midwest Symposium on Circuits and Systems. "33rd Midwest Symposium on Circuits and Systems: Calgary Convention Centre: Calgary, Alberta, Canada: August 12-15, 1990". Calgary: Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 653-656.

URIhttp://hdl.handle.net/2117/27259

DOI10.1109/MWSCAS.1990.140803

ISBN0-7803-0081-5

Publisher versionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=140803

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