Ponències/Comunicacions de congressos
Enviaments recents
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Body bias generators for ultra low voltage circuits in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialElectronic circuits powered at ultra low voltages (300 mV and below) are desirable for their low energy and power consumption. However, the performance at such low power voltage is severely degraded. FDSOI technology, with ... -
Memristive cellular automata for modeling of epileptic brain activity
(2018)
Text en actes de congrés
Accés obertCellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like ... -
Coupled physarum-inspired memristor oscillators for neuron-like operations
(2018)
Text en actes de congrés
Accés obertUnconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant ... -
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ... -
An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
Reliability issues in RRAM ternary memories affected by variability and aging mechanisms
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertResistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and ... -
Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella
(Marcombo, 1983)
Text en actes de congrés
Accés obertEl objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ... -
Design of a broadband CMOS RF power amplifier to establish device-circuit aging correlations
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper presents the design of a Broadband CMOS RF Power Amplifier, suitable to be stressed at circuit level but with the possibility to be measured both at circuit and at device level. It allows establishing a relation ... -
Exploring the voltage divider approach for accurate memristor state tuning
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialThe maximum exploitation of the favorable properties and the analog nature of memristor technology in future nonvolatile resistive memories, requires accurate multilevel programming. In this direction, we explore the voltage ... -
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAM cells
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés restringit per política de l'editorialRandom Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is ... -
Via-configurable transistors array: a regular design technique to improve ICs yield
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertProcess variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ... -
Heterogeneous memristive crossbar for in-memory computing
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertIt's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways ...
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