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Power- and complexity-aware issue queue designs
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-02-09T14:43:58Z |
dc.date.available | 2017-02-09T14:43:58Z |
dc.date.issued | 2003-09 |
dc.identifier.citation | Abella, J., Canal, R., González, A. Power- and complexity-aware issue queue designs. "IEEE micro", Setembre 2003, vol. 23, núm. 5, p. 50-58. |
dc.identifier.issn | 0272-1732 |
dc.identifier.uri | http://hdl.handle.net/2117/100775 |
dc.description.abstract | The improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem. |
dc.format.extent | 9 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Logic design |
dc.subject.lcsh | Microprocessors |
dc.subject.other | Computer architecture |
dc.subject.other | Microcomputers |
dc.title | Power- and complexity-aware issue queue designs |
dc.type | Article |
dc.subject.lemac | Estructura lògica |
dc.subject.lemac | Microprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/MM.2003.1240212 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1240212/ |
dc.rights.access | Open Access |
local.identifier.drac | 814446 |
dc.description.version | Postprint (published version) |
local.citation.author | Abella, J.; Canal, R.; González, A. |
local.citation.publicationName | IEEE micro |
local.citation.volume | 23 |
local.citation.number | 5 |
local.citation.startingPage | 50 |
local.citation.endingPage | 58 |
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