Articles de revista
Enviaments recents
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Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
(2014-10-01)
Article
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm ... -
Low-power automatic speech recognition through a mobile GPU and a Viterbi accelerator
(2017-04-12)
Article
Accés obertAutomatic speech recognition (ASR) has become a core technology for mobile devices. Delivering real-time and accurate ASR has a huge computational cost, which is challenging to achieve in tightly energy-constrained platforms ... -
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
(2017-03-01)
Article
Accés obertBio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, ... -
Executing algorithms with hypercube topology on torus multicomputers
(1995-08)
Article
Accés obertMany parallel algorithms use hypercubes as the communication topology among their processes. When such algorithms are executed on hypercube multicomputers the communication cost is kept minimum since processes can be ... -
Exploiting narrow values for soft error tolerance
(2006-07)
Article
Accés obertSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ... -
Reliability: fallacy or reality?
(2007-11)
Article
Accés obertAs chip architects and manufacturers plumb ever-smaller process technologies, new species of faults are compromising device reliability, following an introduction by the authors debate whether reliability is a legitimate ... -
Thread partitioning and value prediction for exploiting speculative thread-level parallelism
(2004-02)
Article
Accés obertSpeculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ... -
Understanding the thermal implications of multicore architectures
(2007-08)
Article
Accés obertMulticore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations ... -
Reducing branch delay to zero in pipelined processors
(1993-03)
Article
Accés obertA mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ... -
Randomized cache placement for eliminating conflicts
(1999-02)
Article
Accés obertApplications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required ... -
Refueling: Preventing wire degradation due to electromigration
(2008-12)
Article
Accés obertElectromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing ... -
Control speculation for energy-efficient next-generation superscalar processors
(2006-03)
Article
Accés obertConventional front-end designs attempt to maximize the number of "in-flight" instructions in the pipeline. However, branch mispredictions cause the processor to fetch useless instructions that are eventually squashed, ...
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