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dc.contributor.authorPujol Torramorell, Roger
dc.contributor.authorTabani, Hamid
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorHassan, Mohamed
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2021-07-13T12:59:50Z
dc.date.available2021-07-13T12:59:50Z
dc.date.issued2021
dc.identifier.citationPujol, R. [et al.]. Empirical evidence for MPSoCs in critical systems: The case of NXP's T2080 cache coherence. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2021 Design, Automation & Test in Europe (DATE 2021): 01–05 February 2021, virtual conference". IEEE, 2021, p. 1162-1165.
dc.identifier.urihttp://hdl.handle.net/2117/349215
dc.description.abstractThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the MPSoC system due to the unobvious and/or insufficiently documented behavior of some key hardware features. Confidence on those features can only be regained by building specific tests to both, assess whether their behavior matches specifications and unveil their behavior when it is not fully known a priori. In this work, we introduce a systematic approach that constructs this thorough understanding of the MPSoC architecture-- and assess against its specification in processor documentation -- with a focus on the cache coherence protocol in the avionics-relevant NXP T2080 architecture as our use-case. Our approach covers all transitions in the MESI cache coherence protocol, with emphasis on the coherence between DMA and processing cores. We build evidence of their behavior based on available debug support and performance monitors. Our analysis discloses unexpected behavior for coherence-related notifications as well as some hardware monitors.
dc.description.sponsorshipThis work has been partially supported by the Spanish Ministry of Science and Innovation under grant PID2019-107255GB; the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 878752 (MASTECS) and the European Research Council (ERC) grant agreement No. 772773 (SuPerCom); the HiPEAC Network of Excellence; and the Natural Sciences and Engineering Research Council of Canada (NSERC).
dc.language.isoeng
dc.publisherIEEE
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.lcshAvionics
dc.subject.lcshEmbedded computer systems
dc.subject.otherCritical real-time
dc.subject.otherEmbedded systems
dc.subject.otherMPSoCs
dc.subject.otherCache coherence
dc.titleEmpirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
dc.typeConference lecture
dc.subject.lemacMultiprocessadors
dc.subject.lemacAviònica
dc.subject.lemacSistemes incrustats (Informàtica)
dc.identifier.doi10.23919/DATE51398.2021.9474078
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9474078
dc.rights.accessOpen Access
local.identifier.drac31867656
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-107255GB-C22/ES/UPC-COMPUTACION DE ALTAS PRESTACIONES VIII/
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/878752/EU/Multicore Analysis Service and Tools for Embedded Critical Systems/MASTECS
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/772773/EU/Sustainable Performance for High-Performance Embedded Computing Systems/SuPerCom
local.citation.authorPujol, R.; Tabani, H.; Abella, J.; Hassan, M.; Cazorla, F.
local.citation.contributorDesign, Automation and Test in Europe Conference and Exhibition
local.citation.publicationNameProceedings of the 2021 Design, Automation & Test in Europe (DATE 2021): 01–05 February 2021, virtual conference
local.citation.startingPage1162
local.citation.endingPage1165


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