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Dcache Warn: an I-fetch policy to increase SMT efficiency
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Fernandez Garcia, Enrique |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-12-15T09:52:54Z |
dc.date.available | 2017-12-15T09:52:54Z |
dc.date.issued | 2004 |
dc.identifier.citation | Cazorla, F., Ramírez, A., Valero, M., Fernández, E. Dcache Warn: an I-fetch policy to increase SMT efficiency. A: IEEE International Parallel and Distributed Processing Symposium. "18th International Parallel and Distributed Processing Symposium, 2004: proceedings". New Mexico: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 74-83. |
dc.identifier.isbn | 0-7695-2132-0 |
dc.identifier.uri | http://hdl.handle.net/2117/112124 |
dc.description.abstract | Simultaneous multithreading (SMT) processors increase performance by executing instructions from multiple threads simultaneously. These threads share the processor's resources, but also compete for them. In this environment, a thread missing in the L2 cache may allocate a large number of resources for a long time, causing other threads to run much slower than they could. To prevent this problem we should know in advance if a thread is going to miss in the L2 cache. L1 misses are a clear indicator of a possible L2 miss. However, to stall a thread on every L1 miss is too severe, because not all L1 misses lead to an L2 miss, and this would cause an unnecessary stall and resource under-use. Also, to wait until an L2 miss is declared and squash the thread to free up the allocated resources is too expensive in terms of complexity and reexecuted instructions. We propose a novel fetch policy, which we call DWarn. DWarn uses L1 misses as indicators of L2 misses, giving higher priority to threads with no outstanding L1 misses. DWarn acts on L1 misses, before L2 misses happen in a controlled manner to reduce resource under-use and to avoid harming a thread when L1 misses do not lead to L2 misses. Our results show that DWarn outperforms previously proposed policies, in both throughput and fairness, while requiring fewer resources and avoiding instruction reexecution. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Cache memory |
dc.subject.lcsh | Simultaneous multithreading processors |
dc.subject.other | Multiprocessing systems |
dc.subject.other | Multi-threading |
dc.subject.other | Cache storage |
dc.subject.other | Instruction sets |
dc.subject.other | Resource allocation |
dc.title | Dcache Warn: an I-fetch policy to increase SMT efficiency |
dc.type | Conference report |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Memòria cau |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/IPDPS.2004.1303005 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1303005/ |
dc.rights.access | Open Access |
local.identifier.drac | 2363307 |
dc.description.version | Postprint (published version) |
local.citation.author | Cazorla, F.; Ramírez, A.; Valero, M.; Fernández, E. |
local.citation.contributor | IEEE International Parallel and Distributed Processing Symposium |
local.citation.pubplace | New Mexico |
local.citation.publicationName | 18th International Parallel and Distributed Processing Symposium, 2004: proceedings |
local.citation.startingPage | 74 |
local.citation.endingPage | 83 |