CAP - Grup de Computació d'Altes Prestacions
En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.
The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.
The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.
Collections
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Altres [1]
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Articles de revista [258]
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Capítols de llibre [28]
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Llibres [3]
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Reports de recerca [56]
Recent Submissions
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Studying the impact of the Full-Network embedding on multimodal pipelines
(IOS Press, 2018)
Article
Open AccessThe current state of the art for image annotation and image retrieval tasks is obtained through deep neural network multimodal pipelines, which combine an image representation and a text representation into a shared embedding ... -
Petri net analysis using boolean manipulation
(Springer, 1994)
Part of book or chapter of book
Open AccessThis paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The state explosion problem is managed ... -
Look-ahead in the two-sided reduction to compact band forms for symmetric eigenvalue problems and the SVD
(2019-02-01)
Article
Open AccessWe address the reduction to compact band forms, via unitary similaritytransformations, for the solution of symmetric eigenvalue problems and the compu-tation of the singular value decomposition (SVD). Concretely, in the ... -
Two-sided orthogonal reductions to condensed forms on asymmetric multicore processors
(2018-10)
Article
Restricted access - publisher's policyWe investigate how to leverage the heterogeneous resources of an Asymmetric Multicore Processor (AMP) in order to deliver high performance in the reduction to condensed forms for the solution of dense eigenvalue and ... -
Static scheduling of the LU factorization with look-ahead on asymmetric multicore processors
(2018-08)
Article
Restricted access - publisher's policyWe analyze the benefits of look-ahead in the parallel execution of the LU factorization with partial pivoting (LUpp) in two distinct “asymmetric” multicore scenarios. The first one corresponds to an actual hardware-asymmetric ... -
Towards an energy-aware framework for application development and execution in heterogeneous parallel architectures
(Springer, 2019)
Part of book or chapter of book
Restricted access - publisher's policyThe Transparent heterogeneous hardware Architecture deployment for eNergy Gain in Operation (TANGO) project’s goal is to characterise factors which affect power consumption in software development and operation for ... -
ECHOFS: a scheduler-guided temporary filesystem to leverage node-local NVMS
Conference report
Open AccessThe growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. The emerging trend of adding ... -
Verification of asynchronous circuits by BDD-based model checking of Petri nets
(Springer, 1995)
Conference report
Open AccessThis paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification ... -
An out-of-the-box full-network embedding for convolutional neural networks
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Conference report
Open AccessFeatures extracted through transfer learning can be used to exploit deep learning representations in contexts where there are very few training samples, where there are limited computational resources, or when the tuning ... -
Time-constrained loop pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Conference report
Open AccessThis paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource requirements. We propose a methodology, called TCLP, based on ... -
A structural encoding technique for the synthesis of asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Conference report
Open AccessThis paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ... -
On the maturity of parallel applications for asymmetric multi-core processors
(Elsevier, 2019-05-01)
Article
Restricted access - publisher's policyAsymmetric multi-cores (AMCs) are a successful architectural solution for both mobile devices and supercomputers. By maintaining two types of cores (fast and slow) AMCs are able to provide high performance under the facility ...
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