CAP - Grup de Computació d'Altes Prestacions
En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.
The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.
The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.
Colecciones
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Altres [1]
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Articles de revista [253]
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Capítols de llibre [26]
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Llibres [3]
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Reports de recerca [56]
Envíos recientes
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A case study for the verification of complex timed circuits: IPCMOS
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Texto en actas de congreso
Acceso abiertoThe verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ... -
Sampled simulation of task-based programs
(Institute of Electrical and Electronics Engineers (IEEE), 2019-02-01)
Artículo
Acceso abiertoSampled simulation is a mature technique for reducing simulation time of single-threaded programs. Nevertheless, current sampling techniques do not take advantage of other execution models, like task-based execution, to ... -
Formal verification of safety properties in timed circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Texto en actas de congreso
Acceso abiertoThe incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ... -
Structural methods to improve the symbolic analysis of Petri nets
(Springer, 1999)
Texto en actas de congreso
Acceso abiertoSymbolic techniques based on BDDs (Binary Decision Diagrams) have emerged as an efficient strategy for the analysis of Petri nets. The existing techniques for the symbolic encoding of each marking use a fixed set of variables ... -
Synthesis of speed-independent circuits from STG-unfolding segment
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Texto en actas de congreso
Acceso abiertoThis paper presents a novel technique for synthesis of speed-independent circuits. It is based on partial order representation of the state graph called STG-unfolding segment. The new method uses approximation technique ... -
Automatic generation of synchronous test patterns for asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Texto en actas de congreso
Acceso abiertoThis paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ... -
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Texto en actas de congreso
Acceso abiertoPresents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ... -
Memory controller for vector processor
(Springer, 2018-11)
Artículo
Acceso abiertoTo manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase ... -
Efficient encoding schemes for symbolic analysis of Petri nets
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Texto en actas de congreso
Acceso abiertoPetri nets are a graph-based formalism appropriate to model concurrent systems such as asynchronous circuits or network protocols. Symbolic techniques based on Binary Decision Diagrams (BDDs) have emerged as one of the ... -
A mathematical formulation of the loop pipelining problem
(Universitat Politècnica de Catalunya (UPC), 1996)
Texto en actas de congreso
Acceso abiertoThis paper presents a mathematical model for the loop pipelining problem that considers several parameters for optimization and supports any combination of resource and timing constraints. The unrolling degree of the loop ... -
A case for malleable thread-level linear algebra libraries: The LU factorization with partial pivoting
(Institute of Electrical and Electronics Engineers (IEEE), 2019-01-31)
Artículo
Acceso abiertoWe propose two novel techniques for overcoming load-imbalance encountered when implementing so-called look-ahead mechanisms in relevant dense matrix factorizations for the solution of linear systems. Both techniques target ... -
Partial order based approach to synthesis of speed-independent circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Texto en actas de congreso
Acceso abiertoThis paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive ...
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