En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

Recent Submissions

  • A path-level exact parallelization strategy for sequential simulation 

    Peredo, Oscar; Baeza, Daniel; Ortiz, Julian; Herrero Zaragoza, José Ramón (2018-01-01)
    Article
    Restricted access - publisher's policy
    Sequential Simulation is a well known method in geostatistical modelling. Following the Bayesian approach for simulation of conditionally dependent random events, Sequential Indicator Simulation (SIS) method draws simulated ...
  • Gestión de contenidos en caches operando a bajo voltaje 

    Ferrerón, Alexandra; Alastruey, Jesús; Suárez Gracía, Dario; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Viñals Yúfera, Víctor (2016)
    Conference report
    Open Access
    La eficiencia energética de las caches en chip puede mejorarse reduciendo su voltaje de alimentación (Vdd ). Sin embargo, este escalado de Vdd está limitado a una tensión Vddmin por debajo de la cual algunas celdas SRAM ...
  • Selección de contenidos basada en reuso para caches compartidas en exclusión 

    Díaz Maag, Javier; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Ibáñez Marín, Pablo Enrique; Llaberia Griño, José María (2015)
    Conference report
    Open Access
    Publicaciones previas revelan que el flujo de referencias que llega a la cache compartida (SLLC) de un chip multiprocesador muestra poca localidad temporal. Sin embargo, muestra localidad de reuso, es decir, los bloques ...
  • A comparison of cache hierarchies for SMT processors 

    Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
    Conference report
    Open Access
    In the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such ...
  • An adaptive controller to save dynamic energy in LP-NUCA 

    Suárez Gracía, Dario; Monreal Arnal, Teresa; Viñals Yúfera, Víctor (Universidad de La Laguna. Servicio de Publicaciones, 2011)
    Conference report
    Open Access
    Portable devices often demand powerful processors to run computing intensive applications, such as video playing or gaming, and ultra low en-ergy consumption to extend device uptime. Such con-flicting requirements are hard ...
  • Analyzing the impact of communication imbalance in high-speed networks 

    Utrera Iglesias, Gladys Miriam; Gil, Marisa; Martorell Bofill, Xavier (2017-12-21)
    Article
    Restricted access - publisher's policy
    In this work we analyze the communication load imbalance generated by irregular-data applications running in a multi-node cluster. Experimental approaches to diminish communication load imbalance are evaluated using a ...
  • El proyecto EDINSOST: inclusión de los ODS en la educación superior 

    Sánchez Carracedo, Fermín; Segalàs Coral, Jorge; Cabré Garcia, José M.; Climent Vilaró, Joan; López Álvarez, David; Martín Escofet, Carme; Vidal López, Eva María (2017-11)
    Article
    Open Access
    En este artículo se presenta el primer resultado del proyecto EDINSOST: un mapa de la competencia Sostenibilidad para el Grado de Ingeniería Informática, fácilmente adaptable a cualquier titulación de Grado en Ingeniería ...
  • LightDock: a new multi-scale approach to protein-protein docking 

    Jimenez Garcia, Brian; Roel Touris, Jorge; Romero Durana, Miguel; Vidal Espinar, Miquel; Jiménez González, Daniel; Fernández Recio, Juan (2018-01)
    Article
    Restricted access - publisher's policy
    Motivation: Computational prediction of protein-protein complex structure by docking can provide structural and mechanistic insights for protein interactions of biomedical interest. However, current methods struggle with ...
  • Oblivious routing schemes in extended generalized fat tree networks 

    Rodríguez Herrera, Germán; Minkenberg, Cyriel; Beivide Palacio, Ramon; Luijten, Ronald P.; Labarta Mancho, Jesús José; Valero Cortés, Mateo (IEEE Computational Intelligence Society, 2009)
    Conference report
    Open Access
    A family of oblivious routing schemes for fat trees and their slimmed versions is presented in this work. First, two popular oblivious routing algorithms, which we refer to as S-mod-k and D-mod-k, are analyzed in detail. ...
  • Selección del tamaño del banco de registros y de la política de asignación de recursos en procesadores SMT 

    Alastruey, Jesús; Monreal Arnal, Teresa; Cazorla Almeida, Francisco Javier; Viñals Yúfera, Víctor; Valero Cortés, Mateo (Thomson Editores Spain, 2007)
    Conference report
    Open Access
    Este trabajo estudia el impacto del tamaño del banco de registros físico (BRF) en el rendimiento de procesadores Simultaneous Multithreading (SMT). Como es bien conocido, el BRF es un componente crítico en este tipo de ...
  • Automatic generation of workload profiles using unsupervised learning pipelines 

    Buchaca Prats, David; Bernal García, Josep Lluis; Carrera Pérez, David (2017-12-27)
    Article
    Open Access
    The complexity of resource usage and power consumption on cloud-based applications makes the understanding of application behavior through expert examination difficult. The difficulty increases when applications are seen ...
  • A scalable synthetic traffic model of Graph500 for computer networks analysis 

    Fuentes Sáez, Pablo; Benito, Mariano; Vallejo, Enrique; Bosque Orero, José Luis; Beivide Palacio, Ramon; Anghel, Andreea; Rodríguez Herrera, Germán; Gusat, Mitch; Minkenberg, Cyriel; Valero Cortés, Mateo (2017-12-25)
    Article
    Restricted access - publisher's policy
    The Graph500 benchmark attempts to steer the design of High-Performance Computing systems to maximize the performance under memory-constricted application workloads. A realistic simulation of such benchmarks for architectural ...

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