CAP - Grup de Computació d'Altes Prestacions

 

En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

Enviaments recents

  • Low-latency multi-threaded ensemble learning for dynamic big data streams 

    Marron, Diego; Ayguadé Parra, Eduard; Herrero Zaragoza, José Ramón; Read, Jesse; Bifet, Albert (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Text en actes de congrés
    Accés obert
    Real–time mining of evolving data streams involves new challenges when targeting today’s application domains such as the Internet of the Things: increasing volume, velocity and volatility requires data to be processed ...

  • Formalization of block pruning: reducing the number of cells computed in exact biological sequence comparison algorithms 

    De Sandes, Edans; Teodoro, George; Walter, Maria Emilia; Martorell Bofill, Xavier; Ayguadé Parra, Eduard; Melo, Alba (Wiley Heyden, 2018-05-01)
    Article
    Accés restringit per política de l'editorial
    Biological sequence comparison algorithms that compute the optimal local and global alignments calculate a dynamic programming (DP) matrix with quadratic time complexity. The DP matrix H is calculated with a recurrence ...

  • An approach to task-based parallel programming for undergraduate students 

    Ayguadé Parra, Eduard; Jiménez González, Daniel (2018-03-07)
    Article
    Accés obert
    This paper presents the description of a compulsory parallel programming course in the bachelor degree in Informatics Engineering at the Barcelona School of Informatics, Universitat Politècnica de Catalunya UPC-BarcelonaTech. ...

  • Approaching simulation to modelers: a user interface for large-scale demographic simulation 

    Montañola Sales, Cristina; Casanovas Garcia, Josep; Onggo, Bhakti S. S.; Cela Espín, José M.; Kaplan Marcusan, Adriana (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Comunicació de congrés
    Accés obert
    Agent-based modeling is one of the promising modeling tools that can be used in the study of population dynamics. Two of the main obstacles hindering the use of agent-based simulation in practice are its scalability when ...

  • Demographic agent-based simulation of Gambians immigrants in Spain 

    Montañola Sales, Cristina; Casanovas Garcia, Josep; Kaplan Marcusan, Adriana; Cela Espín, José M. (2014)
    Text en actes de congrés
    Accés obert
    Changes in our society have created a challenge for policymakers, who confront a need of tools to evaluate the possible effects of their policies. Agent-based modelling and simulation is a promising methodology which can ...

  • Evaluating A+B=K conditions in constant time 

    Cortadella Fortuny, Jordi; Llaberia Griñó, José M. (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Text en actes de congrés
    Accés obert
    The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ...

  • Characterizing and improving the performance of many-core task-based parallel programming runtimes 

    Bosch, Jaume; Tan, Xubin; Álvarez Martínez, Carlos; Jiménez González, Daniel; Martorell Bofill, Xavier; Ayguadé Parra, Eduard (2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Parallel task-based programming models like OpenMP support the declaration of task data dependences. This information is used to delay the task execution until the task data is available. The dependences between tasks are ...

  • EMVS: Embedded Multi Vector-core System 

    Hussain, Tassadaq; Haider, Amna; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard (2018-06)
    Article
    Accés restringit per política de l'editorial
    With the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications. The existing embedded HPC ...

  • Reuse Detector: improving the management of STT-RAM SLLCs 

    Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
    Article
    Accés restringit per política de l'editorial
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...

  • Skip RNN: learning to skip state updates in recurrent neural networks 

    Campos Camunez, Victor; Jou, Brendan; Giró Nieto, Xavier; Torres Viñals, Jordi; Chang, Shih-Fu (2018)
    Comunicació de congrés
    Accés obert
    Recurrent Neural Networks (RNNs) continue to show outstanding performance in sequence modeling tasks. However, training RNNs on long sequences often face challenges like slow inference, vanishing gradients and difficulty ...

  • Asynchronous and exact forward recovery for detected errors in iterative solvers 

    Jaulmes, Luc Etienne; Casas, Marc; Moreto Planas, Miquel; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (2018-03-19)
    Article
    Accés obert
    Current trends and projections show that faults in computer systems become increasingly common. Such errors may be detected, and possibly corrected transparently, e.g. by Error Correcting Codes (ECC). For a program to be ...

  • A template system for the efficient compilation of domain abstractions onto reconfigurable computers 

    Shafiq, Muhammad; Pericàs Gleim, Miquel; Ayguadé Parra, Eduard (2011)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a ...

Mostra'n més