Exploració per autor "Abella Ferrer, Jaume"
Ara es mostren els items 56-75 de 212
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Efficient cache architectures for reliable hybrid voltage operation using EDC codes
Maric, Bojan; Abella Ferrer, Jaume; Valero Cortés, Mateo (2013)
Text en actes de congrés
Accés obertSemiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have ... -
Empirical evidence for MPSoCs in critical systems: The case of NXP’s T2080 cache coherence
Pujol Torramorell, Roger; Tabani, Hamid; Abella Ferrer, Jaume; Hassan, Mohamed; Cazorla Almeida, Francisco Javier (IEEE, 2021)
Comunicació de congrés
Accés obertThe adoption of complex MPSoCs in critical real-time embedded systems mandates a detailed analysis their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the ... -
En-route: on enabling resource usage testing for autonomous driving frameworks
Alcon, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Kosmidis, Leonidas; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2020-03)
Text en actes de congrés
Accés obertSoftware resource usage testing, including execution time bounds and memory, is a mandatory validation step during the integration of safety-related real-time systems. However, the inherent complexity of Autonomous Driving ... -
Enabling unit testing of already-integrated AI software systems: The case of Apollo for autonomous driving
Alcón Doganoc, Miguel; Tabani, Hamid; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertThe advanced AI-based software used for autonomous driving comprises multiple highly-coupled modules that are data and control dependent. Deploying those already-integrated software frameworks makes unit testing, a fundamental ... -
End-to-end QoS for the open source safety-relevant RISC-V SELENE platform
Andreu Cerezo, Pablo; Hernández Luz, Carles; Picornell Sanjuan, Tomás; López Rodríguez, Pedro; Alcaide Portet, Sergi; Bas Jalón, Francisco; Benedicte Illescas, Pedro; Chang, Feng; Cabo Pitarch, Guillem; Fuentes Díaz, Francisco Javier; Abella Ferrer, Jaume (arXiv, 2022)
Text en actes de congrés
Accés obertThis paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENEplatform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach ... -
Energy efficient object detection for automotive applications with YOLOv3 and approximate hardware
Fornt Mas, Jordi; Fontova Muste, Pau; Caro Roca, Martí; Abella Ferrer, Jaume; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertDeep neural networks are the dominant models for perception tasks in the automotive domain, but their high computational complexity makes it difficult to execute them in real time with an acceptable power consumption on ... -
EOmesh: combined flow balancing and deterministic routing for reduced WCET estimates in embedded real-time systems
Cardona Nadal, Jordi; Abella Ferrer, Jaume; Hernández Luz, Carles; Cazorla Almeida, Francisco Javier (2018-07-17)
Article
Accés obertThe increasing performance needs in critical real-time embedded systems (CRTES) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance ... -
ePAPI: Performance Application ProgrammingInterface for Embedded Platforms
Giesen, Jeremy; Mezzetti, Enrico; Abella Ferrer, Jaume; Fernández, Enrique; Cazorla, Francisco J. (2019)
Comunicació de congrés
Accés obertPerformance Monitoring Counters (PMCs) have been traditionally used in the mainstream computing domain to perform debugging and optimization of software performance. PMCs are increasingly considered in embedded time-critical ... -
EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application
Mezzetti, Enrico; Fernandez, Mikel; Bardizbanyan, Alen; Agirre, Irune; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
Comunicació de congrés
Accés obertMeasurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ... -
EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis
Ziccardi, Marco; Mezzetti, Enrico; Vardanega, Tullio; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2016-01-18)
Comunicació de congrés
Accés obertMeasurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ... -
Execution time distributions in embedded safety-critical systems using extreme value theory
del Castillo, Joan; Padilla, Maria; Abella Ferrer, Jaume; Cazorla, Francisco J. (Inderscience, 2017)
Article
Accés obertSeveral techniques have been proposed to upper-bound the worst-case execution time behaviour of programs in the domain of critical real-time embedded systems. These computing systems have strong requirements regarding the ... -
Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study
González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
Comunicació de congrés
Accés restringit per política de l'editorialTime-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ... -
Fitting processor architectures for measurement-based probabilistic timing analysis
Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Hernández, Carles; Gianarro, Andrea; Broster, Ian; Cazorla Almeida, Francisco Javier (2016-11-01)
Article
Accés obertThe pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case ... -
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262
Agirre, Irune; Cazorla, Francisco J.; Abella Ferrer, Jaume; Hernandez, Carles; Mezzetti, Enrico; Azkarate-askasua, Mikel; Vardanega, Tullio (IEEE, 2018-09-01)
Accés obertCar manufacturers relentlessly replace or augment the functionality of mechanical subsystems with electronic components. Most such subsystems (e.g., steer-by-wire) are safety related, hence, subject to regulation. ISO-26262, ... -
FOCSI: A new layout regularity metric
Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
Report de recerca
Accés obertDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ... -
Fuse: A technique to anticipate failures due to degradation in ALUs
Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; Unsal, Osman Sabri; Ergin, Oguz; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
Text en actes de congrés
Accés obertThis paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder ... -
Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier
Pujol, Roger; Tabani, Hamid; Kosmidis, Leonidas; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla, Francisco J. (2019)
Comunicació de congrés
Accés obertDeep learning-based solutions and, in particular, deep neural networks (DNNs) are at the heart of several functionalities in critical-real time embedded systems (CRTES) from vision-based perception (object detection and ... -
GPU devices for safety-critical systems: a survey
Pérez Cerrolaza, Jon; Abella Ferrer, Jaume; Kosmidis, Leonidas; Calderón Torres, Alejandro Josué; Cazorla Almeida, Francisco Javier; Flores Barroso, José Luis (Association for Computing Machinery (ACM), 2023-07)
Article
Accés obertGraphics Processing Unit (GPU) devices and their associated software programming languages and frameworks can deliver the computing performance required to facilitate the development of next-generation high-performance ... -
GPU4S: Embedded GPUs in Space
Kosmidis, Leonidas; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertFollowing the same trend of automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from both control and payload parts of ... -
GPU4S: Embedded GPUs in Space - Latest project updates
Kosmidis, Leonidas; Rodríguez Ferrandez, Iván; Jover Álvarez, Álvaro; Alcaide Portet, Sergi; Lachaize, Jérôme; Abella Ferrer, Jaume; Notebaert, Olivier; Cazorla Almeida, Francisco Javier; Steenari, David (2020-09)
Article
Accés obertFollowing the trend of other safety-critical industries like automotive and avionics, the space domain is witnessing an increase in the on-board computing performance demands. This raise in performance needs comes from ...