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Fitting processor architectures for measurement-based probabilistic timing analysis

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10.1016/j.micpro.2016.07.014
 
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hdl:2117/100471

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Kosmidis, LeonidasMés informació
Quiñones, Eduardo
Abella Ferrer, JaumeMés informació
Vardanega, Tullio
Hernández, Carles
Gianarro, Andrea
Broster, Ian
Cazorla Almeida, Francisco Javier
Document typeArticle
Defense date2016-11-01
Rights accessOpen Access
Attribution-NonCommercial-NoDerivs 4.0 International
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 4.0 International
ProjectCOMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
RYC-2013-14717 (MINECO-RYC-2013-14717)
PROXIMA - Probabilistic real-time control of mixed-criticality multicore and manycore systems (EC-FP7-611085)
Abstract
The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case execution time (WCET) analysis of software programs - which is often required, especially for programs at the highest levels of integrity - an even harder challenge. State-of-the-art WCET analysis techniques are hampered by the soaring cost and complexity of obtaining accurate knowledge of the internal operation of advanced processors and the difficulty of relating data obtained from measurement observations with reliable worst-case behaviour. This frustrating conundrum calls for novel solutions, with low intrusiveness on development practice. Measurement-Based Probabilistic Timing Analysis (MBPTA) techniques offer the opportunity to simultaneously reduce the cost of acquiring the knowledge needed for computing reliable WCET bounds and gain increased confidence in the representativeness of measurement observations. This paper describes the changes required in the design of several high-performance features - massively used in modern processors - to meet MBPTA requirements.
CitationKosmidis, L., Quiñones, E., Abella, J., Vardanega, T., Hernández, C., Gianarro, A., Broster, I., Cazorla, F. Fitting processor architectures for measurement-based probabilistic timing analysis. "Microprocessors and microsystems", 1 Novembre 2016, vol. 47, núm. Part B, p. 287-302. 
URIhttp://hdl.handle.net/2117/100471
DOI10.1016/j.micpro.2016.07.014
ISSN0141-9331
Publisher versionhttp://www.sciencedirect.com/science/article/pii/S0141933116300977
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  • Computer Sciences - Articles de revista [272]
  • Departament d'Arquitectura de Computadors - Articles de revista [957]
  • CAP - Grup de Computació d'Altes Prestacions - Articles de revista [380]
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