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A polymorphic register file for matrix operations
dc.contributor.author | Ciobanu, Catalin |
dc.contributor.author | Kuzmanov, Georgi |
dc.contributor.author | Gaydadjiev, Georgi |
dc.contributor.author | Ramírez Bellido, Alejandro |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2011-02-11T14:21:08Z |
dc.date.available | 2011-02-11T14:21:08Z |
dc.date.created | 2010 |
dc.date.issued | 2010 |
dc.identifier.citation | Ciobanu, C. [et al.]. A polymorphic register file for matrix operations. A: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. "2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010)". Samos: IEEE Computer Society Publications, 2010, p. 241-249. |
dc.identifier.isbn | 978-1-4244-7937-5 |
dc.identifier.uri | http://hdl.handle.net/2117/11342 |
dc.description.abstract | Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization which allows dynamic creation of a variable number of multidimensional registers of arbitrary sizes referred to as a Polymorphic Register File. Our objective is to evaluate the performance benefits of the proposed organization. Simulation results using real applications (Floyd and CG) suggest speedups of up to 3 times compared to the Cell SPU for Floyd and 2 times compared to a one dimensional vectorized version of the sparse matrix vector multiplication. Moreover, in the same experimental context, a large reduction in the number of executed instructions of up to 3000 times for Floyd and 2000 times for sparse matrix vector multiplication is achieved. |
dc.format.extent | 9 p. |
dc.language.iso | eng |
dc.publisher | IEEE Computer Society Publications |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal::Processament de matrius (arrays) |
dc.subject.lcsh | File organization (Computer science) |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.lcsh | Matrix (Organization) |
dc.subject.other | Cell |
dc.subject.other | Polymorphism |
dc.subject.other | Vector ISA |
dc.subject.other | Vector processors |
dc.subject.other | Vector register file |
dc.title | A polymorphic register file for matrix operations |
dc.type | Conference report |
dc.subject.lemac | Matrius (Matemàtica) -- Processament de dades |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/ICSAMOS.2010.5642059 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5642059 |
dc.rights.access | Open Access |
local.identifier.drac | 4984221 |
dc.description.version | Postprint (published version) |
local.citation.author | Ciobanu, C.; Kuzmanov, G.; Gaydadjiev, G.; Alex Ramirez |
local.citation.contributor | International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation |
local.citation.pubplace | Samos |
local.citation.publicationName | 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010) |
local.citation.startingPage | 241 |
local.citation.endingPage | 249 |