En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

Enviaments recents

  • Fuzzy memoization for floating-point multimedia applications 

    Álvarez Martínez, Carlos; Corbal San Adrián, Jesús; Valero Cortés, Mateo (2005-07)
    Article
    Accés obert
    Instruction memoization is a promising technique to reduce the power consumption and increase the performance of future low-end/mobile multimedia systems. Power and performance efficiency can be improved by reusing instances ...
  • Explaining dynamic cache partitioning speed ups 

    Moreto Planas, Miquel; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-01)
    Article
    Accés obert
    Cache partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, ...
  • Coarse grain parallelization of deep neural networks 

    González Tallada, Marc (2016-08-01)
    Article
    Accés restringit per política de l'editorial
    Deep neural networks (DNN) have recently achieved extraordinary results in domains like computer vision and speech recognition. An essential element for this success has been the introduction of high performance computing ...
  • Enlarging instruction streams 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
    Article
    Accés obert
    The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...
  • A methodology for user-oriented scalability analysis 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María; Marí, Carme (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    Scalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ...
  • A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Text en actes de congrés
    Accés obert
    The paper proposes an algorithm for computing symmetric eigenvalues and eigenvectors that uses a one-sided Jacobi approach and is targeted to a multicomputer in which nodes can be arranged as a two-dimensional mesh with ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Text en actes de congrés
    Accés obert
    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

    Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...
  • Alya: Multiphysics engineering simulation toward exascale 

    Vázquez, Mariano; Houzeaux, Guillaume; Koric, Seid; Artigues, Antoni; Aguado Sierra, Jazmin; Arís Sánchez, Ruth; Mira, Daniel; Calmet, Hadrien; Cucchietti, Fernando; Owen, Herbert; Taha, Ahmed; Dering Burness, Evan; Cela Espín, José M.; Valero Cortés, Mateo (Elsevier, 2016-05)
    Article
    Accés restringit per política de l'editorial
    Alya is a multi-physics simulation code developed at Barcelona Supercomputing Center (BSC). From its inception Alya code is designed using advanced High Performance Computing programming techniques to solve coupled problems ...
  • A runtime heuristic to selectively replicate tasks for application-specific reliability targets 

    Subasi, Omer; Yalcin, Gulay; Zyulkyarov, Ferad; Unsal, Osman Sabri; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    In this paper we propose a runtime-based selective task replication technique for task-parallel high performance computing applications. Our selective task replication technique is automatic and does not require ...

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