En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

Enviaments recents

  • Delaying physical register allocation trought virtual-physical registers 

    Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Text en actes de congrés
    Accés obert
    Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
  • Optimizing program locality through CMEs and GAs 

    Vera, Xavier; Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs ...
  • A performance analysis of a mimetic finite difference scheme for acoustic wave propagation on GPU platforms 

    Otero Calviño, Beatriz; Frances, Jorge; Rodriguez Cruz, Robert; Rojas, Otilio; Solano, Freysimar; Guevara-Jordan, Juan (2017-02-01)
    Article
    Accés restringit per política de l'editorial
    Realistic applications of numerical modeling of acoustic wave dynamics usually demand high-performance computing because of the large size of study domains and demanding accuracy requirements on simulation results. Forward ...
  • Reducing branch delay to zero in pipelined processors 

    González Colás, Antonio María; Llaberia Griñó, José M. (1993-03)
    Article
    Accés obert
    A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ...
  • REPP-H: Runtime Estimation of Power and Performance on Heterogeneous Data Centers 

    Nishtala, Rajiv; Martorell Bofill, Xavier; Petrucci, Vinicius; Mossé, Daniel (2016)
    Text en actes de congrés
    Accés obert
    Modern data centers increasingly demand improved performance with minimal power consumption. Managing the power and performance requirements of the applications is challenging because these data centers, incidentally or ...
  • Adaptive runtime-assisted block prefetching on chip-multiprocessors 

    García Flores, Víctor; Rico Carro, Alejandro; Villavieja Prados, Carlos; Carpenter, Paul M.; Navarro Mas, Nacho; Ramirez, Alex (2016-04-29)
    Article
    Accés restringit per política de l'editorial
    Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the ...
  • Improving I/O performance through an in-kernel disk simulator 

    González Férez, Pilar; Piernas Canovas, Juan; Cortés, Toni (2016-10-01)
    Article
    Accés restringit per política de l'editorial
    This paper presents two mechanisms that can significantly improve the I/O performance of both hard and solid-state drives for read operations: KDSim and REDCAP. KDSim is an in-kernel disk simulator that provides a framework ...
  • A confidence assessment of WCET estimates for software time randomized caches 

    Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...
  • Emergent behaviors in the Internet of things: The ultimate ultra-large-scale system 

    Roca, Damian; Nemirovsky, Daniel; Nemirovsky, Mario; Milito, Rodolfo; Valero Cortés, Mateo (2016-11)
    Article
    Accés obert
    To reach its potential, the Internet of Things (IoT) must break down the silos that limit applications' interoperability and hinder their manageability. Doing so leads to the building of ultra-large-scale systems (ULSS) ...
  • The death star challenge: an ambitious and motivating engineering project to promote astronautics and transform society's vision about space research 

    Pérez Poch, Antoni; Sánchez Carracedo, Fermín; López Álvarez, David; Alier Forment, Marc (2016)
    Comunicació de congrés
    Accés obert
    The race to put a person on the Moon motivated and captivated the imagination of USA society and the community worldwide. This led to an unprecedented investment in science, technology and the space program, which ...

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