En aquest grup s´investiga en tècniques que permeten millorar l´eficiència dels sistemes de computació d?altes prestacions. Aquest objectiu es tracta des de perspectives diverses que requereixen un cert grau de cooperació: arquitectura del sistema uniprocessador i multiprocessador, compilador, sistema operatiu, eines d´anàlisi, visualització i predicció, algorismes i aplicacions. Per mesurar l´eficiència es consideren mètriques que van més enllà del temps d´execució dels programes. En particular es consideren aspectes relacionats amb el disseny del sistema (cicle d´operació, àrea i consum de potència del processador i la jerarquia de memòria, escalabilitat de l´organització uniprocessador i multiprocessador), amb la verificació funcional dels sistemes, amb la facilitat i la portabilitat del model de programació i amb el rendiment en entorns multiprogramats i distribuïts, entre altres.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

The group aims to improve the efficiency of high-performance computing systems. To that end, it employs a variety of approaches that require a certain level of cooperation and integration: microarchitecture and multiprocessor architecture, compilers, operating systems, analysis, visualisation and prediction tools, algorithms and applications. When measuring efficiency, in addition to the traditional approach that takes the execution time into account, we use metrics that consider design factors such as cycle time, area and power dissipation of the processor and memory hierarchy, scalability of the microarchitecture and multiprocessor organisation, system correctness, portability and ease of use of programming models, and performance when running on multiuser, multiprogrammed and distributed environments, among others.

http://futur.upc.edu/CAP

Enviaments recents

  • Modeling seismic wave propagation using staggered-grid mimetic finite differences 

    Solano, Freysimar; Guevara-Jordan, Juan; González, Carlos; Rojas, Otilio; Otero Calviño, Beatriz (2017-04-12)
    Article
    Accés obert
    Mimetic finite difference (MFD) approximations of continuous gradient and divergente operators satisfy a discrete version of the Gauss-Divergente theorem on staggered grids. On the mimetic approximation of this integral ...
  • Non-consistent dual register files to reduce register pressure 

    Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Text en actes de congrés
    Accés obert
    The continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative ...
  • Out-of-order commit processors 

    Cristal Kestelman, Adrián; Ortega, Daniel; Llosa Espuny, José Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Modern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ...
  • Direct instruction wakeup for out-of-order processors 

    Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ...
  • A conflict-free memory banking architecture for fast VOQ packet buffers 

    García Vidal, Jorge; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    In order to support the enormous growth of the Internet, innovative research in every router subsystem is needed. We focus our attention on packet buffer design for routers supporting high-speed line rates. More specifically, ...
  • SEDEA: A sensible approach to account DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    As the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy ...
  • On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers 

    García Vidal, Jorge; March Hermo, María Isabel; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    We address the design of a packet buffer for future high-speed routers that support line rates as high as OC-3072 (160 Gb/s), and a high number of ports and service classes. We describe a general design for hybrid DRAM/SRAM ...
  • Prophet/critic hybrid branch prediction 

    Falcón Samper, Ayose Jesús; Stark, Jared; Ramírez Bellido, Alejandro; Lai, Konrad; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    This paper introduces the prophet/critic hybrid conditional branch predictor, which has two component predictors that play the role of either prophet or critic. The prophet is a conventional predictor that uses branch ...
  • Implicit vs. explicit resource allocation in SMT processors 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Garcia, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    In a simultaneous multithreaded (SMT) architecture, the front end of a superscalar is adapted in order to be able to fetch from several threads while the back end is shared among the threads. In this paper, we describe ...
  • Enabling SMT for real-time embedded systems 

    Cazorla Almeida, Francisco Javier; Knijnenburg, Peter M.W.; Sakellariou, Rizos; Fernandez Prieto, Enrique; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    In order to deal with real time constraints, current embedded processors are usually simple in-order processors with no speculation capabilities to ensure that execution times of applications are predictable. However, ...
  • Dynamically controlled resource allocation in SMT processors 

    Cazorla Almeida, Francisco Javier; Ramírez Bellido, Alejandro; Valero Cortés, Mateo; Fernandez Prieto, Enrique (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for ...
  • A module-based cell processor simulator 

    Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Rodenas, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2006)
    Comunicació de congrés
    Accés obert
    An interesting design alternative to replication-based chip multiprocessors is to create heterogeneous chip multiprocessors composed of several different cores, with one or more of them running the operating system and ...

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