Enviaments recents

  • A distributed processor state management architecture for large-window processors 

    González, Isidro; Galluzzi, Marco; Veidenbaum, Alexander V.; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with ...
  • Performance analysis of sequence alignment applications 

    Sánchez Castaño, Friman; Salamí San Juan, Esther; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
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    Advances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a multi-disciplinary field, including components of ...
  • Resolucion de problemas electromagneticos mediante el metodo de elementos finitos en computadores de paralelismo masivo 

    Cruellas Ibarz, Juan Carlos; Duffo Ubeda, Núria (Universitat Politècnica de València, 1993)
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  • A case for merging the ILP and DLP paradigms 

    Quintana Rodríguez, Francisca; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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    The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved ...
  • Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance 

    Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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    Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ...
  • Effective usage of vector registers in advanced vector architectures 

    Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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    This paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the ...
  • Hybrid transactional memory to accelerate safe lock-based transactions 

    Vallejo, Enrique; Harris, Tim; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2008)
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    To reduce the overhead of Software Transactional Memory (STM) there are many recent proposals to build hybrid systems that use architectural support either to accelerate parts of a particular STM algorithm (Ha-TM), or ...
  • A dynamic scheduler for balancing HPC applications 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ...
  • Who shot optical packet switching? 

    Almeida Amazonas, José Roberto de; Santos Boada, Germán; Solé Pareta, Josep (Institute of Electrical and Electronics Engineers (IEEE), 2017)
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    Looking at the volume of publications dealing with Optical Packet (OPS) and those dealing with Elastic Optical Networking (EON) in the period from 2000 to 2016, one clearly can observe that between 2004 and 2009 there is ...
  • Predicting access to persistent objects through static code analysis 

    Touma, Rizkallah; Queralt Calafat, Anna; Cortés, Toni; Pérez Hernandez, María S. (Springer, 2017)
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    In this paper, we present a fully-automatic, high-accuracy approach to predict access to persistent objects through static code analysis of object-oriented applications. The most widely-used previous technique uses a simple ...

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