Enviaments recents

  • Exploiting a new level of DLP in multimedia applications 

    Corbal San Adrián, Jesús; Valero Cortés, Mateo; Espasa Sans, Roger (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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    This paper proposes and evaluates MOM: a novel ISA paradigm targeted at multimedia applications. By fusing conventional vector ISA approaches together with more recent SIMD-like (Single Instruction Multiple Data) ISAs (such ...
  • Quantifying the benefits of SPECint distant parallelism in simultaneous multithreading architectures 

    Ortega Fernández, Daniel; Martel Pérez, Iván; Krishnan, Venkata; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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    We exploit the existence of distant parallelism that future compilers could detect and characterise its performance under simultaneous multithreading architectures. By distant parallelism we mean parallelism that cannot ...
  • Command vector memory systems: high performance at low cost 

    Corbal San Adrián, Jesús; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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    The focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from ...
  • Effective usage of vector registers in decoupled vector architectures 

    Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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    The paper presents a study of the impact of reducing the vector register size in a decoupled vector architecture. In traditional in-order vector architectures long vector registers have typically been the norm. The authors ...
  • A Quick View on Current Techniques and Machine Learning Algorithms for Big Data Analytics 

    Berral García, Josep Lluís (Institute of Electrical and Electronics Engineers (IEEE), 2016)
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    Big-data is an excellent source of knowledge and information from our systems and clients, but dealing with such amount of data requires automation, and this brings us to data mining and machine leaming techniques. In ...
  • Access to vectors in multi-module memories 

    Valero Cortés, Mateo; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1994)
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    The poor bandwidth obtained from memory when conflicts arise in the modules or in the interconnection network degrades the performance of computers. Address transformation schemes, such as interleaving, skewing and linear ...
  • A methodology for user-oriented scalability analysis 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María; Marí, Carme (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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    Scalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ...
  • A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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    The paper proposes an algorithm for computing symmetric eigenvalues and eigenvectors that uses a one-sided Jacobi approach and is targeted to a multicomputer in which nodes can be arranged as a two-dimensional mesh with ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

    Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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    The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...

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