Envíos recientes

  • A case for merging the ILP and DLP paradigms 

    Quintana Rodríguez, Francisca; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Texto en actas de congreso
    Acceso abierto
    The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved ...
  • Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance 

    Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Texto en actas de congreso
    Acceso abierto
    Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ...
  • Effective usage of vector registers in advanced vector architectures 

    Villa, Luis; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Texto en actas de congreso
    Acceso abierto
    This paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the ...
  • Hybrid transactional memory to accelerate safe lock-based transactions 

    Vallejo, Enrique; Harris, Tim; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2008)
    Texto en actas de congreso
    Acceso abierto
    To reduce the overhead of Software Transactional Memory (STM) there are many recent proposals to build hybrid systems that use architectural support either to accelerate parts of a particular STM algorithm (Ha-TM), or ...
  • A dynamic scheduler for balancing HPC applications 

    Boneti, Carlos; Gioiosa, Roberto; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Texto en actas de congreso
    Acceso abierto
    Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be alleviated by modern MT processors that provide mechanisms for ...
  • Predicting access to persistent objects through static code analysis 

    Touma, Rizkallah; Queralt Calafat, Anna; Cortés, Toni; Pérez Hernandez, María S. (Springer, 2017)
    Texto en actas de congreso
    Acceso abierto
    In this paper, we present a fully-automatic, high-accuracy approach to predict access to persistent objects through static code analysis of object-oriented applications. The most widely-used previous technique uses a simple ...
  • A block algorithm for the algebraic path problem and its execution on a systolic array 

    Núñez, Fernando J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1989)
    Texto en actas de congreso
    Acceso abierto
    The solution of the algebraic path problem (APP) for arbitrarily sized graphs by a fixed-size systolic array processor (SAP) is addressed. The APP is decomposed into two subproblems, and SAP is designed for each one. Both ...
  • Fast speculative address generation and way caching for reducing L1 data cache energy 

    Nicolaescu, Dan; Salamat, Babak; Veidenbaum, Alex; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Texto en actas de congreso
    Acceso abierto
    L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to ...
  • Efficient data sharing on heterogeneous systems 

    García-Flores, Víctor; Ayguadé Parra, Eduard; Peña, Antonio J. (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    General-purpose computing on GPUs has become more accessible due to features such as shared virtual memory and demand paging. Unfortunately it comes at a price, and that is performance. Automatic memory management is ...
  • A directive-based approach to perform persistent checkpoint/restart 

    Maroñas, Marcos; Mateo, Sergi; Beltran Querol, Vicenç; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Texto en actas de congreso
    Acceso restringido por política de la editorial
    Exascale platforms require support for resilience capabilities due to increasing numbers of components and associated error rates. In this paper, we present a new directive-based approach to perform application-level ...

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