Enviaments recents

  • ParaView + Alya + D8tree: Integrating high performance computing and high performance data analytics 

    Artigues, Antoni; Cugnasco, Cesare; Becerra Fontal, Yolanda; Cucchietti, Fernando; Houzeaux, Guillaume; Vázquez, Mariano; Torres Viñals, Jordi; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (Elsevier, 2017)
    Article
    Accés obert
    Large scale time-dependent particle simulations can generate massive amounts of data, making it so that storing the results is often the slowest phase and the primary time bottleneck of the simulation. Furthermore, analysing ...
  • Access to streams in multiprocessor systems 

    Valero Cortés, Mateo; Peirón Guardia, Montse; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Text en actes de congrés
    Accés obert
    When accessing streams in vector multiprocessor machines, degradation in the interconnection network and conflicts in the memory modules are the factors that reduce the efficiency of the system. In this paper, we present ...
  • A systolic algorithm for the fast computation of the connected components of a graph 

    Núñez, Fernando J.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Text en actes de congrés
    Accés obert
    The authors consider the description of a systolic algorithm to solve the connected-component problem. It is executed in a ring topology with N processors, requiring O(Nlog N) time without regard to the graph's sparsity. ...
  • Analysis and simulation of multiplexed single-bus networks with and without buffering 

    Llaberia Griñó, José M.; Valero Cortés, Mateo; Herrada Lillo, Enrique; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 1985)
    Text en actes de congrés
    Accés obert
    Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. ...
  • A two level load/store queue based on execution locality 

    Pericàs Gleim, Miquel; Cristal Kestelman, Adrián; Cazorla, Francisco; González García, Rubén; Veidenbaum, Alexander V; Jiménez, Daniel A.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ...
  • Computing size-independent matrix problems on systolic array processors 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1986)
    Text en actes de congrés
    Accés obert
    A methodology to transform dense to band matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of solutions to problems with any given ...
  • Agent-based simulation of large population dynamics 

    Montañola Sales, Cristina; Casanovas Garcia, Josep; Cela Espín, José M.; Onggo, B.S.S.; Kaplan Marcusan, Adriana (2013)
    Comunicació de congrés
    Accés obert
    Agent-based modelling and simulation is a promising methodology that can be used in the study of population dynamics. One of the main obstacles hindering the use of agent-based simulation in practice is its scalability, ...
  • Parallel simulation of large population dynamics 

    Montañola Sales, Cristina; Casanovas Garcia, Josep; Cela Espín, José M.; Kaplan Marcusan, Adriana (2013)
    Comunicació de congrés
    Accés obert
    Agent-based modeling and simulation is a promising methodology that can be used in the study of population dynamics. We present the design and development of a simulation tool which provides basic support for modeling and ...
  • CellSim: a validated modular heterogeneous multiprocessor simulator 

    Cabarcas Jaramillo, Felipe; Rico Carro, Alejandro; Ródenas Picó, David; Martorell Bofill, Xavier; Ramírez Bellido, Alejandro; Ayguadé Parra, Eduard (Thomson Editores Spain, 2007)
    Text en actes de congrés
    Accés obert
    As the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance, computer architects have decided to use ...
  • Virtual registers 

    González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ...

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